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AR# 39764

Aurora 64B/66B v5.1 - Release Notes and Known Issues for ISE Design Suite 12.4


This Answer Record contains the Release Notes for the Aurora 64B/66B v5.1 Core, released in ISE Design Suite 12.4, and includes the following:
  • New Features  
  • Bug Fixes 
  • Known Issues  
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf


New Features

  • ISE 12.4 software support
  • AXI4-Streaming Protocol support
  • Virtex-6 HXT/GTH VHDL support

Bug Fixes

  • C_REFCLK_FREQUENCY value error between Linux and Windows OS
  • Data loss due to misalignment of RXData from CC logic
  • Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert
  • Virtex-6 MMCM does not lock
  • GTX_TX_CLK_SOURCE should point to TXPLL for Simplex TX designs
  • TXPLLKDET is not high in Virtex-6 GT Wrapper

Known Issues

  • Virtex-6 HXT/GTH max lanes supported is 8 lanes
  • Virtex-6 HXT/GTH selection of quads should be consecutive -There cannot be an unused quad between two used quads
  • Virtex-6 HXT/GTH solutions are pending for hardware validation
  • Virtex-5 specific contents exists in User Guide/Data Sheet
AR# 39764
Date Created 01/05/2011
Last Updated 02/19/2015
Status Active
Type Release Notes
  • Aurora 64B/66B