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AR# 39803

12.4/13.4/14.7 MAP-ERROR:MapLib:973 - Tri-state buffers are not supported in this architecture

Description

I receive the following error during the MAP process:

ERROR:MapLib:973 - Tri-state buffers are not supported in this architecture.

How can I resolve it?

Solution

The root cause for the problem is that there is an internal 3-state buffer (BUFT) inferred. 

However, there is no such architecture in the Xilinx device.

Usually this error is seen when Synplify Pro is used to synthesize the whole design or submodules.

  • When using Synplify Pro to synthesize the whole design, MAP reports this error on the bi-directional top level ports if the "disable I/O Insertion" option is checked/enabled.
    When I/O insertion is disabled, Synplify Pro infers BUFT on the top level ports instead of OBUFT or IOBUF, which causes the error.
    To resolve the problem, uncheck the "disable I/O Insertion" option.
     
  • When using Synplify Pro to synthesize the submodule which is to be used in the top module as a black box, the "disable I/O Insertion" option has to be checked.
    If the tri-state logic coding of the bi-directional port is in the submodule, Synplify Pro infers BUFT in the submodule netlist, which causes the MAP error.
    To resolve this problem, put the 3-state signal in the top module.

      Submodule code:

......
inout [31:0] ad_b;
assign ad_b = (tri_en)? 32'bz : tri_output_d ;

......

     To resolve the issue, the signal ad_b should be moved to top module.

  • Another workaround is to instantiate one "IOBUF" instead of behavioral code, thus preventing BUFT inference.
AR# 39803
Date Created 12/20/2010
Last Updated 09/30/2014
Status Active
Type Error Message
Tools
  • ISE Design Suite - 12.3
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 14
  • Less