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AR# 39909

13.1 XPS - "ERROR:PhysDesignRules:1385" about FSL core


The following error is received during Bitgen stage in Xilinx Platform Studio (XPS).How to resolve it?

ERROR:PhysDesignRules:1385 - Invalid configuration (incorrect pin connections and/or modes) on block:<fsl_demo_core_0_to_microblaze_0/fsl_demo_core_0_to_microblaze_0/Using_FIFO.Sync_FIFO_Gen.Use_Control.Sync_FIFO_I1/Sync_FIFO_I.srl_fifo_i.FSL_FIFO/FIFO_RAM[32].SRL16E_I>:<LUT_OR_MEM6>. For RAMMODE programming set with DPRAM32 or SPRAM32 or SRL16 the DI2 input pin must be connected.


This error occurs because the "FSL_M_Control" signal is not connected to any sources in CustomIP's HDL code and the tool does not correctly optimize the SRL component which is driven by this signal.

To work around this problem, unset the "Propagate Control Bit" option in FSL buses when the FSL_M_Control signal is not used.
AR# 39909
Date Created 06/30/2011
Last Updated 05/19/2012
Status Active
Type Error Message
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1