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AR# 3992

FPGA Express - How do I implement a Synchronous Reset in VHDL or Verilog?

Description

Keywords: FPGA Express, Foundation Express, set, reset, SR, SS, counter

Urgency: Standard

General Description:
When Synchronous Reset or Set is implemented in a synchronous element like a
register or a counter, synthesizing in FPGA Express will cause the following message
to appear:

Inferred memory devices in process
in routine jct_vhd line 18 in file
'H:/mydesign/counter.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
| COUNT_reg | Flip-flop | 8 | Y | N | N | N | N | N |
===============================================================================

COUNT_reg (width 8)
--------------------
set/reset/toggle: none


** No synchronous reset is reported.

Solution

With this code, the synchronous reset is implemented with an AND gate at the D input
of registers (see FDR implementation in the Libraries Guide). This is functionally correct,
but does not used the dedicated features of Xilinx devices.

To use the Synchronous Set/Reset pin of a flip-flop, use the Synopsys Attributes library.
The sync_set_reset attribute is attached to single-bit signals with the attribute construct
(VHDL) or compiler directive (Verilog).

This must be declared at the top of every VHDL entity that will use the sync_set_reset
attribute:

library synopsys;
use synopsys.attributes.all;

Then, attach the "sync_set_reset" attribute to the reset signal in every entity. Here is the
section of VHDL code that will infer the synchronous reset:


architecture COUNT_ARCH of COUNTER is

signal COUNT: STD_LOGIC_VECTOR (7 downto 0);
attribute sync_set_reset of RESET: signal is "true";

begin

process (CLK, RESET)
begin
if (CLK'event and CLK='1') then
if (RESET='1') then
COUNT <= "00000000";
else
COUNT <= COUNT + 1;
end if;
end if;
end process;


No library needs to be defined for Verilog. You will need to declare the attribute for every
Verilog module. Here is the section of Verilog code that will infer the synchronous reset:

//synopsys sync_set_reset "RESET"

always @(posedge CLK)
if (RESET)
COUNT = 8'b00000000;
else
COUNT = COUNT + 1;



You will see the following change in the FPGA Express report:

Inferred memory devices in process
in routine jct_vhd line 18 in file
'H:/mydesign/counter.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | AR | AS | SR | SS | ST |
===============================================================================
| COUNT_reg | Flip-flop | 8 | Y | N | N | Y | N | N |
===============================================================================

COUNT_reg (width 8)
--------------------
Sync-reset: RESET


For a synchronous SET, simply assign the output to 1 instead of 0 when the SET signal
is active.
AR# 3992
Date Created 05/29/1998
Last Updated 08/11/2003
Status Archive
Type General Article