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AR# 39929

MIG v3.6-v3.61 Virtex-6 DDR3 - tRC violations occur in simulation when # of banks is increased

Description

MIG v3.6-v3.61 Virtex-6 DDR3 designs will fail with tRC violations during simulation only for x16 components if the # of Banks is increased to greater than 4.

The following code changes are required to increase the # of Banks:
parameter BM_CNT_WIDTH =3; (in sim_tb_top.v)
parameter nBANK_MACHS =5; (in memc_ui_top.v)

Simulation Error Messages seen:
# Calibration Done
# sim_tb_top.comp_inst.mem_rnk[0].mem_16.gen_mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 57512599.0 ps INFO: Refresh
# sim_tb_top.comp_inst.mem_rnk[0].mem_16.gen_mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 57622599.0 ps INFO: Activate bank 0 row 0000
# sim_tb_top.comp_inst.mem_rnk[0].mem_16.gen_mem.gen_mem[0].u_comp_ddr3.chk_err: at time 57632599.0 ps ERROR: tRC violation during Activate to bank 0
# sim_tb_top.comp_inst.mem_rnk[0].mem_16.gen_mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 57632599.0 ps ERROR: Activate Failure. Bank 0 must be Precharged.

Solution

This issue occurs because the BM_CNT_WIDTH parameter is not being passed from the sim_tb_top module to the example_top. The workaround is to pass the BM_CNT_WIDTH to the example_top instantiation in sim_tb_top.v as shown below:

example_top #
(
.nCK_PER_CLK (nCK_PER_CLK),
.tCK (tCK),
.RST_ACT_LOW (RST_ACT_LOW),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.......


This is fixed in 13.1 with MIG v3.7.
AR# 39929
Date Created 02/16/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG