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AR# 39946

Spartan-6 - Converting from the Spartan-6 -4 Speed File to the New -3 Speed File


In ISE 12.4, the Spartan-6 FPGA -3 speed file was improved to be almost identical to the -4 speed file. As a result, the -4 speed grade is being discontinued in XCN11008. Designs targeted to the -4 speed file should be updated to target the new -3 speed file for lower cost. Only the Spartan-6 LXT devices (LX25T, LX45T, LX75T, LX100T, LX150T) were offered in the -4 speed grade, and only for Commercial operating conditions. The new -3 speed grade supports all Spartan-6 devices, and is offered in both Commercial and Industrial operating conditions.

The new -3 speed file provides approximately 12% higher performance and is applicable to all existing standard production Spartan-6 devices.


There are some minor differences between the -4 and the new -3 speed files. The majority of these differences are less than 0.1ns and are not expected to impact the ability of successful -4 designs to meet timing with the new -3 speed file. The majority of the differences between the -3 and -4 speed files can be seen by using the speedprint command and comparing the results. The -4 production speed file is v1.11 or later, which is available in ISE 12.2 software with the 12.2 Speed Files Patch or later. The data sheet DS162 provides a subset of the speed file parameters. As of DS162 revision 1.12 February 11, 2011, the -4 speed file is no longer shown in the data sheet. The -4 data sheet numbers were identical to those shown for the -3 with the following exceptions:

FGTPDRPCLK GTP transceiver DCLK (DRP clock) maximum frequency
-4 = 160 MHz, -3 = 120 MHz

TODCK D1/D2 pins Setup
-4 = 0.60 ns, -3 = 0.81 ns
TOSRCK SR pin Setup
-4 = 0.68 ns, -3 = 0.70 ns

-4 = 0.14 ns, -3 = 0.17 ns
TTAP8 Tap 8 delay
-4 = 292 ps, -3 = 322 ps

TSRCK SR input setup on flip-flops
-4 = 0.34 ns, -3 = 0.41 ns
TCEO Delay from CE input to latch outputs
-4 = 0.53 ns, -3 = 0.60 ns

CLB Shift Register:
TCECK CE input setup
-4 = 0.27 ns, -3 = 0.29 ns

Block RAM:
TRCCK_EN Block RAM Enable Input (EN) setup
-4 = 0.21 ns, -3 = 0.22 ns

TICKOF Global Clock and OUTFF without DCM or PLL in XC6SLX45T
-4 = 6.42 ns, -3 = 6.49 ns

TPHFD Global Clock Hold without DCM or PLL in XC6SLX45T
-4 = 1.88 ns, -3 = 1.95 ns

TPSDCM Global Clock Setup with DCM in System-Synchronous Mode in XC6SLX150T
-4 = 1.51 ns, -3 = 1.55 ns

TPSDCM0 Global Clock Setup with DCM in Source-Synchronous Mode in XC6SLX150T
-4 = 0.66 ns, -3 = 0.69 ns

TPSDCMPLL Global Clock Setup with DCM and PLL in System-Synchronous Mode in XC6SLX150T
-4 = 1.35 ns, -3 = 1.39 ns

The data sheet provides a subset of the speed file parameters. Other similar differences will be found in related timing parameters. The speedprint command can be used to see a more complete list of timing parameters.

Designs should be re-implemented in ISE 12.4 software or later and timing constraints used to verify that the new -3 speed file meets application requirements.If re-implementation is not feasible, timing analysis alone could be re-checked using the -3 speed file from ISE 12.4 software or later. Bitstreams are 100% compatible between the -4 and -3 speed grades. A design targeted to the -4 speed grade can be programmed into a -3 device after verifying timing.A design targeted to any production -3 speed grade can beprogrammed into a -4 device without modification.

Related Answers
The improved -3 speed file does not apply to Engineering Samples; see (Xilinx Answer 39545).
Spartan-6 speed file revision history; see (Xilinx Answer 33282).
Resolution of setup regression, see (Xilinx Answer 39754)

AR# 39946
Date Created 01/06/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 12.4