UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39960

Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC - Synopsys VCS back-annotated timing simulations time out

Description

Using the Synopsys VCS simulator to perform back-annotated timing simulations of certain configurations of the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC can result in the following error:

ERROR - Testbench timed out

Specifically, the TEMAC_SINGLE SecureIP model's EMACPHYTXGMIIMIICLKOUT clock output fails to toggle in some cases, resulting in a lack of transmitter operation. 

This is due to pulse-swallowing of the PHYEMACGTXCLK input within the X_TEMAC_SINGLE simprim instance, and is limited to timing simulations when using the Synopsys VCS simulator.

This issue has been seen with the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v1.5 and v2.1 wrappers in ISE 12.x and ISE 13.x.

Solution

To work around this problem, use another supported simulator to perform back-annotated timing simulations.

Alternatively, if use of the Synopsys VCS simulator is desired, you can do one of the following:

  • Address pulse swallowing behavior according to (Xilinx Answer 9872)
     
  • Remove SDF timing data back-annotation by removing the "-sdf" argument from the vcs command (for example in the provided simulate_vcs.sh script)

Linked Answer Records

Master Answer Records

AR# 39960
Date Created 02/16/2011
Last Updated 09/08/2014
Status Active
Type General Article
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper