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AR# 39974

LogiCORE LTE PUCCH Receiver - Release Notes and Known Issues


This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE LTE PUCCH Receiver Core. 

The following information is listed for each version of the core: 
  • New Features 
  • Resolved Issues
  • Known Issues


LogiCORE LTE PUCCH Receiver v1.0  

Initial Release in ISE 13.1 software.

New Features 
  • Available for Virtex-7, Kintex-7, Virtex-6 and Virtex-5 devices
  • Physical Uplink Control Channel for 3GPP TS 36.211
  • Supports all format types including Mixed Format
  • Supports both normal and shortened slots
  • Supports normal and extended Cyclic Prefix
  • Bit-accurate C model provided with core 
  • Fully optimized for speed and area 
  • Fully synchronous design using a single clock 

Resolved Issues
  • None

Known Issues (ISE) 
  • None

Known Issues (Vivado)

  • (Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with error: Error: Failed to find design work <Core name>?
AR# 39974
Date Created 02/10/2011
Last Updated 05/29/2013
Status Active
Type Release Notes
  • 3GPP LTE PUCCH Receiver