Below is a checklist to verify when instantiating a black boxed component in VHDL or Verilog. This is only done if you have a netlist (NGC, NGO, or EDF) that represents the blackbox:
VHDL:
- Ensure that the port names are consistent between the component declaration and the instantiation.
- Ensure that the port widths are consistent between the component declaration and the instantiation.
- Ensure that the port directions are consistent between the component declaration and the instantiation.
- Ensure that semicolons are placed after every port except for the last port in the component declaration.
- Ensure that commas are placed after every connection in an instantiation except for the last connection.
- Capitalization only matters if you are instantiating a Verilog module in VHDL.
- In the instantiation, remember that the instance name is before the colon. The component name comes after the colon.
- Component declarations are either placed in a package, or in the same file as the instantiation between the architecture and begin statement.
Verilog:
- Capitalization must be consistent
- A module declaration without any synthesizable code must also be compiled so that XST knows the port information.
- Ensure that the port names are consistent between the declaration and the instantiation.
- Ensure that the port widths are consistent between the declaration and the instantiation.
- Ensure that the port directions are consistent between the declaration and the instantiation.
- Ensure that commas are placed after every connection except for the last connection.
- In the instantiation, remember that the component name comes before the instance name.
Also remember that XST can read your black boxed component and include all of the statistics into the Final Report. XST has an option called "Read Cores" that enables this.
If an instance is not intended to be black boxed. Please see
(Xilinx Answer 40787)