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AR# 39981

Design Assistant for XST - Help instantiating Xilinx cores


Please refer to this answer record for help instantiating Xilinx cores.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.


When generating Xilinx Cores, Coregen will also generate an instantiation template. This instantiation template is used as a template so that the port names are correctly spelled. It is still up so the user to ensure the following:

  • The signals connected to the ports are the correct width. The instantiation template should state the port widths.
  • VHDL requires component declarations.
  • Verilog will require a module with the port definitions. This file is generated by coregen and may have a behavioral or structural model in the body. This depends on the core that is generated.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38927 Xilinx Solution Center for XST N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39648 Design Assistant for XST - Instantiating modules, primitives, black boxes and Xilinx Cores. N/A N/A
AR# 39981
Date Created 03/15/2011
Last Updated 12/15/2012
Status Active
Type General Article