Solution

TX CLOCKING

Part of the requirement to fix the Delay Aligner issue is that the GTXTXOUTCLK must drive the MMCM directly with no BUFG in the path. By default, in the wrapper, TXOUTCLK already drives the MMCM directly with no BUFG in the path. The only implementation change needed is that the MMCM is restricted to the same region as the MGTs and users must not add a BUFG to move the MMCM out of the region. If users have modified the wrapper to add a BUFG to this path in order to move the MMCM out of the region with the MGTs, it must be removed and the MMCM should be located in the region with the MGT providing TXOUTCLK.

RX CLOCKING

One of the requirements to fix the Delay Aligner issue is that the GTX RXUSRCLK2must be driven by BUFR, which itself is driven by the GTX output clock. By default, in the wrapper, RXUSRCLK2 is already driven by the BUFR.

Delay Aligner Workaround

To disable both the Tx Delay Aligner and Rx Delay Aligner make the following changes.

Step 1
In the instantiation of gtx0_gtx_wrapper_i in the file v6_gtxwizard.vhd change the Generic GTX_POWER_SAVE from "0000000100" to "0000110100"

Modifying the POWER_SAVE attribute will result in software DRC errors in ISE 12.4, 12.3 and 12.2. These same errors occur in simulation as well. (Xilinx Answer 39434) provides a method for working around these errors.

Step 2
In gt_and_clocks.vhd disable the Rx and TX fabric Delay Aligner by making the following changes:

Step 3

Change:

tx_sync_i : TX_SYNC
port map (
TXENPMAPHASEALIGN => txenpmaphasealign,
TXPMASETPHASE => txpmasetphase,
TXDLYALIGNDISABLE => txdlyaligndisable,
TXDLYALIGNRESET => txdlyalignreset,
SYNC_DONE => tx_sync_done,
USER_CLK => txusrclk2,
RESET => tx_sync_reset
);


to:

tx_sync_i : TX_SYNC
port map (
TXENPMAPHASEALIGN => txenpmaphasealign,
TXPMASETPHASE => txpmasetphase,
TXDLYALIGNDISABLE => open,
TXDLYALIGNRESET => txdlyalignreset,
SYNC_DONE => tx_sync_done,
USER_CLK => txusrclk2,
RESET => tx_sync_reset
);

txdlyaligndisable <= '1';



Step 4

Change:

-- Send a grant back to the core when the DRP is ready
process(aux_clk)
begin
if aux_clk'event and aux_clk = '1' then
if (drp_arb_req = '1' and gt_drdy = '1')
or speed_select(1 downto 0) /= "00" then
drp_arb_gnt_i <= '1';
elsif drp_arb_req = '0' then
drp_arb_gnt_i <= '0';
end if;
end if;
end process;


to

drp_arb_gnt_i <= '1';


Step 5

Change:

aligner_lock_i <= aligner_lock when speed_select(5 downto 2) /= "0000" else '1';

to

aligner_lock_i <= '1';

Step 6

Change:

rxdlyalignreset <= reset_aux_clk_r(0) when speed_select(5 downto 2) /= "0000"
else '1';

to

rxdlyalignreset <= '1';

CLOCKING STRUCTURE

To ensure the MMCM is used to compensate for the BUFG delay correctly the MMCM internal dividers need to be used. Therefore the clocking structure as outlined in AR 39430 can not be used for the CPRI IP. It is necessary to use clkout0 to drive the userclk and use a second BUFG to the clkfbout pin and feed the output of the second BUFG to the clkfbin pin input of the MMCM. In example_design/gtx_and_clock directory edit the tx_clk_gen.vhd file as follows

Step 7
Add a signal fbout:

signal fbout : std_logic;


Step 8
Add a BUFG to fb:

clkfb_bufg : bufg
port map (
I => fbout,
O => fb);


Step 9
And on the instantiation of mmcm_adv_inst : MMCM_ADV
change:

(CLKFBOUT => fb,

To:

(CLKFBOUT => fbout,

For Release Notes and Known Issues for 12.2 for the LogiCORE CPRI v3.2, please see (Xilinx Answer 36969).