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AR# 39995

7 Series FPGAs - Built-in Asynchronous FIFO Software Support

Description

ISE Design Suite 13.1 does not support the use of the built-in FIFO block when used in asynchronous clocking mode. The ISEsoftware version13.2 and later do support the built-in FIFO when used in asynchronous clocking mode, but there are some early Kintex-7 FPGAs that have restricted functionality.

Solution

ISE Design Suite13.2

The dual clock built-in FIFO, when used with different read and write clocks (asynchronous clocking), is fully supported beginning in ISE Design Suite13.2.The simulation model has been updated and does correctly reflect the device behavior. However, ISE software version 13.2 will still issue the following warning:

"WARNING:PhysDesignRules - Issue with pin connections and/or configuration on block:<FIFO18E1_INST>:<FIFO18E1_FIFO18E1>. The EN_SYNC attribute is set to FALSE. This version of the software does not accurately model the behavior of the built-in dual-clock FIFO primitive (asynchronous version only) for Xilinx 7 Series FPGAs. The behavior of the 7 Series built-in FIFO will be accurately modeled in a future version of ISE. For more information please visit Xilinx Answer Record 39995 at: http://www.xilinx.com/support/answers/39995.htm."

This warning can be ignored if targeting any device except for Kintex-7 XC7K325T.Kintex-7 XC7K325T devices in the Initial ES program do not support use of the built-in FIFO in asynchronous clocking mode.To find out if your device is affected, reference the letter or errata that accompanied your parts for the exact limitations.

ISE Design Suite 13.1

The dual clock built-in FIFO, when used with different read and write clocks (asynchronous clocking), is not supported in ISE Design Suite13.1.ISE software version 13.1 issues a warning to alert you that the FIFO functionality is not properly supported in asynchronous mode, and is to be changed in future versions of the software.

"WARNING:PhysDesignRules - Issue with pin connections and/or configuration on block:<FIFO18E1_INST>:<FIFO18E1_FIFO18E1>. The EN_SYNC attribute is set to FALSE. This version of the software does not accurately model the behavior of the built-in dual-clock FIFO primitive (asynchronous version only) for Xilinx 7 Series FPGAs. The behavior of the 7 Series built-in FIFO will be accurately modeled in a future version of ISE. For more information please visit Xilinx Answer Record 39995 at: http://www.xilinx.com/support/answers/39995.htm."

Work-around

  • Use ISE Design Suite 13.2.
  • Use the built-in FIFO in synchronous mode (set the EN-SYN attribute to TRUE).
  • Users requiring FIFO capability with different read and write clocks can use the FIFO Generator v8.1and selectthe soft FIFO.
AR# 39995
Date Created 02/28/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3