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AR# 40017

Design Assistant for PCI Express - Why does the configuration space reset when transitioning from D3 to D0

Description

This Answer Record will help you understand why the configuration space is reset when transitioning from a Power Managment state D3 to D0.

NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

Xilinx PCI Express cores will reset the configuration space when transitioning from a D3 state to D0. This is because Xilinx IntegratedPCI Express blocks have the no_soft_reset bit set to 0. According to the PCI Express Base Specification Section 5.3.1.4, the configuration space should reset if the no_soft_reset bit is set to 0 and the endpoint is changing from a D3 state to a D0 state.

Revision History:
10/31/2011 - Initial Release
AR# 40017
Date Created 10/31/2011
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )