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AR# 40037

Virtex-6 - Use RAMB18 with independent read and write width


In Virtex-6 FPGA, a block RAM stores up to 36k bits of data and it can be configured as two independent 18 kilobit RAMs. Each block RAM can be configured as true dual-port (TDP), simple dual-port (SDP) and single port. It can also have independent read width and write width.


When a Block RAM is used in SDP mode the READ and WRITE widths must be equal. Therefore, when a RAMB18 is configured with independent read and write widths with Block Memory Generator (IP core), it cannot choose an SDP and will choose a TDP RAMB36, which causes the BRAM resource to be doubled.

The user can instantiate the RAMB18E1 primitive or the BRAM_SDP_MACRO macro.
AR# 40037
Date 04/14/2011
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
  • Block Memory Generator