We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40111

12.4 System Generator for DSP - AXI-IP System Generator synchronizer block is not inverting active-low ARESETn signal


A problem can occur when using the AXI-IP blocks in System Generator with the ARESETn pin. This problem is related to multi-rate designs that use the Synchronizer block to synchronize the periods of output ports. The reset from the synchronizer block is active high, but the reset for other AXI-IP cores are active low. This can cause the core to be held permanently in reset.

One manifestation of this problem is seen with AXI FIR Compiler v6.x blocks; the reset used to drive the synchronizer blocks derived directly from the ARESETn signal without being inverted. As a result, no output is obtained from the AXI-IP FIR block.


This problem is scheduled to be fixed in version 13.1 of System Generator. 

To work around this issue, do not use the ARESETn reset signal while using version 12.3 or 12.4.

AR# 40111
Date Created 01/17/2011
Last Updated 05/23/2014
Status Archive
Type General Article
  • System Generator for DSP - 12.4
  • System Generator for DSP - 12.3
  • FIR Compiler