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AR# 40119

Design Assistant for XST - Help Resolving "HDLCompiler:1156: Formal port does not exist in entity " error

Description

Refer to this Answer Record for help resolving "HDLCompiler:1156: Formal port <comp_veriloginport> does not exist in entity <low>" errors.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.

Solution

This error message comes when there is a mismatch between name of formal ports used in component/module definition and the ones used while
instantiating them.

What is formal port ?

A formal port is a port that is declared in the module/component/entity header and used in the body of the module/component/entity. See the EXAMPLE for more elaboration.

WHAT NEXT:
Use correct formal port name while instantiating module/component or entity.

EXAMPLE:

Consider the following RTL:

library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity top is
port (vhdlinport : in std_logic;
vhdloutport : out std_logic);
end top;
architecture arch_IncrBindMixedAssoc04_top of top is
component low is
port (comp_veriloginport : in std_logic;
comp_verilogoutport : out std_logic);
end component;

begin
U1 : low
port map (vhdlinport, comp_verilogoutport => vhdloutport);
end ;
configuration config_IncrBindMixedAssoc04_top of top is
for arch_IncrBindMixedAssoc04_top
for U1 : low
port map (comp_veriloginport, verilogoutport => comp_verilogoutport);
end for;
end for;
end config_IncrBindMixedAssoc04_top;

`timescale 1ns/1ns
module low (veriloginport, verilogoutport) ;
input veriloginport ;
output verilogoutport ;
assign verilogoutport = veriloginport;
endmodule

In this example, the formal port declared in the module 'low' are 'veriloginport' and 'verilogoutport'. While the instantiation in the architecture 'arch_IncrBindMixedAssoc04_top', port map uses a port name 'comp_verilogoutport' which is not present in the module 'low'.Using the correct formal port name, i.e. 'verilogoutport' should fix the problem.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38927 Xilinx Solution Center for XST N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40379 Design Assistant for XST Help understanding the XST report to resolve errors\warnings N/A N/A
AR# 40119
Date Created 01/17/2011
Last Updated 12/15/2012
Status Active
Type General Article