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AR# 40181

SPI-4.2 v11.1 - 7 Series core functional and timing simulations might fail to complete DPA due to X propagation from ISERDES


When using the SPI-4.2 v11.1 core targeting Virtex-7 or Kintex-7 FPGA, a reset is needed to the ISERDES to avoid an 'X' on the output of the ISERDES. This reset is required before any core logic looks at the output of ISERDES or the 'X' will continue to be propagated even after a reset to the ISERDES is issued.

In some cases (e.g., using the "DPA Wait for Training Control" core option), the SPI-4.2 v11.1 core might look at the outputs of the ISERDES before the core asserts a reset to the ISERDES, which then causes a loop where inputs back to the ISERDES are calculated based on these X values, thus,causing the ISERDES to continue outputing Xs. This causes all testcases that use this option to fail.


A work-around has been implemented in the SPI-4.2 v11.1 example design testbench.

To temporarily work around this problem,makethe "pl4_startup" testbench module assert SnkDPAPhaseAlignRequest for a short period of time during assertion of Reset_n.

A more permanent fix to the reset logic in the core netlist is going to be added to the v11.2 SPI-4.2 Core scheduled for ISE Design Suite 13.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40640 SPI-4.2 v11.1 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40181
Date Created 02/24/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • SPI-4 Phase 2 Interface Solutions