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AR# 40200

LogiCORE FIR Compiler v6.0 - My core simulation does not match the Latency value in the CORE Generator GUI. Why is that?

Description

My core simulation does not match the Latency value in the CORE Generator GUI. Why is that?

For example,the value given in the Summary page of CORE Generator is less that what is seen in simulation.

Solution

This is a bug in the CORE Generator GUI that will be fixed in the FIR Compiler v6.3. The simulation latency is the correct value.

You should only use the the CORE Generator as a rough estimate, but to get the actual value you need to simulate the core.
It is also recommended that design use the appropriate AXI-4 Streaming handshake signals, as this will account for the latency of the core.

Please see (Xilinx Answer 29138) for a detailed list of LogiCORE IP FIR Compiler Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
29138 LogiCORE IP Finite Impulse Response Compiler (FIR Compiler) - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
29138 LogiCORE IP Finite Impulse Response Compiler (FIR Compiler) - Release Notes and Known Issues N/A N/A
AR# 40200
Date Created 01/21/2011
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • FIR Compiler