We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40221

Spartan-6 - For how long should the BITSLIP in the ISERDES be asserted?


It is not clear from the Spartan-6 FPGA SelectIO Resources User Guide (UG381) how long the BITSLIP should be asserted.

What are the requirements for BITSLIP?


The BITSLIP has to be synchronous to CLKDIV, and it is recommended that it is asserted High for only 1 CLKDIV cycle.

BITSLIP can be held high for consecutive cycles of CLKDIV,which will result in multiple Bitslip operations.

Due to the latency through the ISERDES, in practice you would not issue multiple Bitslips as you would need to monitor the ISERDES output after each Bitslip operation to check if the training pattern has being found.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 40221
Date Created 05/03/2011
Last Updated 02/26/2013
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q