UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40255

14.1 Timing Analyzer - Timing report does not reflect that phase shifts for the DCM

Description

When I change the phase shift numbers for the Digital Clock Manager (DCM), I do not see the change in numbers for the setup and hold calculations for the clock.

Why does this not change?

Solution

If you are doing timing analysis against auto generated constraints, phase shift numbers are not part of the timing analysis.

When you do the analysis with the timing constraints for the design, then the phase shift numbers are taken into consideration when doing the timing analysis.
AR# 40255
Date Created 04/27/2012
Last Updated 05/16/2012
Status Archive
Type Design Advisory
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less