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AR# 40311

MIG v3.7 Virtex-6, Spartan-6 - UCF changes to support Synplify E-2010.09-1-SP2

Description

MIG Virtex-6 and Spartan-6 3.7 supports Synplify E-2010.09-1 as output by the MIG tool. If you would like to use the latest version (Synplify E-2010.09-1-SP2), this Answer Record describes the necessary changes. For MIG designs that are synthesized with SynplifyE-2010.09-1-SP2, generate statements in the Verilog code result in different hierarchical node names as with previous Synplify versions.Therefore, some of the node names in the UCF have to be changed to reflect this new naming convention. This issue exists only for Verilog designs and is scheduled to be fixed in ISE softwarerelease 13.2.

Solution

The following are the changes requiredfor the UCF:

  • The changes are only required for Verilog designs;VHDL designs do not have this issue
  • The changeis required in the UCF file alone (example_top.ucf or <component_name.ucf>)
  • The genblk* should be removed from the constraint as shown below

Virtex-6 FPGA UCF changes:

UCF constraints generated by MIG:

INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X1Y301";
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_odelay_cpt"LOC = "IODELAY_X1Y301";

Changed UCF constraint to makeassignments compatible withSynplifyE-2010.09-1-SP2:

INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"LOC = "OLOGIC_X1Y301";
INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"LOC = "IODELAY_X1Y301";

Spartan-6 FPGA UCF changes:

UCF constraints generated by MIG:

NET

"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/genblk*.gen_term_calib.mcb_soft_calibration_top_inst/
mcb_soft_calibration_inst/cke_train" TIG; ## This path exists for DDR2 only

Changed UCF constraint to makeassignments compatible withSynplifyE-2010.09-1-SP2:

NET

"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/
mcb_soft_calibration_inst/cke_train" TIG; ## This path exists for DDR2 only

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40311
Date Created 02/01/2011
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6Q
  • Spartan-6 LXT
  • More
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
IP
  • MIG