This issue can be worked around by implementing the following steps:
1. Prevent any masters from accessing memory until the AXI_V6_DDRx controller has completed its calibration. One way this can be accomplished is to use the phy_init_done output signal to hold the associated master in reset.
2. The following patch can be extracted to the project pcore directory. Restart XPS. MIG users can replace their existing hdl files from the version in the zip.
http://www.xilinx.com/txpatches/pub/applications/misc/ar40388.zip This issue isscheduledto be fixed in EDK 13.2.