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AR# 40399

Spartan-6 FPGA SP605 Evaluation Kit - Board Debug Checklist

Description

The SP605 Evaluation Board Checklistis useful to debug board-related issues and to determine if a Boards RMA is the next step.

Solution

1. Jumper Settings
2. Board Power / LEDs
3. JTAG Initialization
4. JTAG Configuration
5. Slave SelectMAP Configuration
6. Master BPI Configuration
7. Slave Serial Configuration
8. Master Serial / SPI Configuration
9. System ACE Configuration
10. IBERT
11. PCIe
12. Multiboot
13. MIG / DDR3

  1. Verify Default Jumper/Switch Settings

    Jumpers:
    FMC JTAG BYPASS
    J19 Jump 1-2
    SFP Module
    J22 Jump 1-2
    J44 Jump 1-2
    SPI Memory Select
    J46 Jump 1-2
    SystemACE CF Error LED
    J60 Jump 1-2
    Switches:
    SW1.2 ON
    SW1.1 OFF
    S1.4 ON
    S1.3 OFF
    S1.2 OFF
    S1.1 OFF
    S2.4 OFF
    S2.3 OFF
    S2.2 OFF
    S2.1 OFF
  2. Power ON Test LEDs Status (below) are indications of board health
    Proves basic functioning of the board is OK.
    1. Check the status of the following LEDs at Power ON, if not, try reset the TI power controllers using the XML script. See (Xilinx Answer 39037):
      • DS1 - FMC Power Good - ON
      • DS14 - 12V Power On - ON
      • DS15 - DDR3 1.5V Power On - ON
      • DS18 - System ACE CF Error (blinks red with No CF card)
      • DS19 - MGT_AVCC Power On - ON
    2. Check 6 Ethernet LEDs near RJ45 Ethernet jack P1. Cycle Power ON and OFF and see that all LEDs blink.
    3. If these LEDs above (a & b) are not lit at power on, you may need to re-program the TI Power Controllers on your board.  This can be done using the Texas Instruments Fusion Digital Power Manufacturing Tool software package, the Texas Instruments USB Interface Adapter EVM, and the appropriate XML script.
      For more details, see (Xilinx Answer 37561); and see (Xilinx Answer 56811) for information on the appropriate XML files to be used (these are board specific).
      If you do not have a TI USB Interface Adapter EVM, you can follow the steps in (Xilinx Answer 54022) to order one.
    4. Check 12V Power LED is Green. If not, follow these steps:




    5. Check the JTAG chain is initialized properly. If not, follow these steps:



    6. Verify switch SW1 settings:
      SW1.2 = OFF
      SW1.1 = ON
      default setting for SW1
      (JTAG port is always available to the FPGA regardless of the mode pin settings.)
    7. Verify FMC bypass jumper position J19.
      Pin 1 and 2 to be connected by jumper in case FMC card is not present.
      If using an FMC card, still try with jumpers on pin 1 and 2 of J19.
      If problems occur when FMC LPC connector included, but SP605 works when FMC LPC connector excluded, then there might be an issue with the FMC connector.
    8. Verify use of a supported OS.
  3. If JTAG chain not initialized in iMPACT:
    • Check cable drivers are loaded on host PC.
    • Check system propertiesand environment variables.
    • USB port enabled?
    • iMPACT tools correctly installed?
    • There are 2 USB mini-B connectors on the board; USB-JTAG and USB-UART. Verify that USB-JTAG is being used to initialize the chain.
    • Check step2d. above.
  4. JTAG chain initializes, but JTAG configuration fails:
    • Check 12V Power LED is Green; if not, see step 2c. above.
    • Verify SW1 settings; see step 2e. above.
    • Check step 2f. above.
    • Check step 2g. above.
  5. Problems during Slave SelectMAP configuration:
    • Check 12V Power LED is Green; if not, see step 2c. above.
    • Verify SW1 settings for SelectMAP:
      SW1.2 = ON
      SW1.1 = OFF
    • Ensure configuration from the System ACE card is disabled by setting switch S1.4 = OFF.
    • Restore Flash contents using factory supplied default image; see xtp061.pdf for instructions.
  6. Problems during Master BPI configuration:
    • Check 12V Power LED is Green; if not, see step 2c. above.
    • Verify SW1 settings:
      SW1.2 = OFF
      SW1.1 = OFF
    • Ensure configuration from the System ACE card is disabled by setting switch S1.4 = OFF.
    • Restore Flash contents using factory supplied default image; see xtp061.pdf for instructions.
  7. Problems during Slave Serial configuration:
    • Check 12V Power LED is Green; if not, see step 2c. above.
    • Verify SW1 settings:
      SW1.2 = ON
      SW1.1 = ON
    • Ensure configuration from the System ACE card is disabled by setting switch S1.4 = OFF.
  8. Problems during Master Serial / SPI configuration:
    • Check 12V Power LED is Green; if not, see step2c. above.
    • Verify SW1 settings:
      SW1.2 = OFF
      SW1.1 = ON
    • Ensure configuration from System ACE card is disabled by setting switch S1.4 = OFF.
  9. Problems during System ACE configuration:
    • Check 12V Power LED is Green; if not, see step 2c. above.
    • Verify S1 settings: S1.4 = ON.
    • Verify CF image address is set correctly using S1.1, S1.2, and S1.3.
    • Verify CF card is inserted properly in its socket.
    • Format and restore Compact Flash card with factory supplied default image; see rdf0031.zip.
  10. Configuration is OK, IBERT not working:
    • Verify S1.4 switch set to OFF.
    • Check SMA loop back cable used correctly (if using MGT loopback). When using SMA cable, connect J32 to J34 and J33 to J35.
    • Download and run rdf0036.zip and xtp066.pdf (whichever version is appropriate for Silicon and Software version; i.e., xtp066_13.2_c.pdf and rdf0036_13.2_c.zip for 13.2 ISE and Production Silicon) from the SP605 Reference Designs page.
    • Read and follow guidelines in xtp066.pdf.
    • SP605 - IBERT Known Issues: (Xilinx Answer 36775) and (Xilinx Answer 39514).
  11. Configuration is OK, PCIE-Gen1 interface not working:
    • Verify SW1 settings
      SW1.2 = OFF
      SW1.1 = ON
    • Ensure PC power is connected to J27 and Power switch is turned off. Do not use PCI connector PC power supply. Do not use both SP605 Power brick connector (J60) AND 4-pin ATX connector at the same time
    • Ensure PCIE core was created correctly (refer toUG654).
    • Download and run rdf0035.zip and xtp065.pdf (whichever version is appropriate for Silicon and Software version; i.e., xtp065_13.2_cpdf and rdf0035_13.2_c.zip for 13.2 software and Production Silicon)
    • Read and follow guidelines in xtp065.pdf.
    • SP605 - PCIE Known Issues: (Xilinx Answer 35594) and (Xilinx Answer 34404).
  12. Configuration is OK, Multiboot not working:
    • Verify SW1 settings:
      SW1.2 = OFF
      SW1.1 = ON
    • Verify steps taken to program SP605 with Multiboot bitstream in iMPACT (refer to UG380).
    • Download and run rdf0028.zip and xtp059.pdf (whichever version is appropriate for Silicon and Software version; i.e., xtp059_13.2_c.pdf and rdf0028_13.2_c.zip for 13.2 software and Production Silicon)
    • Read and follow guidelines in xtp059.pdf
  13. Configuration is OK, MIG / DDR3 interface not working:
    • Ensure DDR3 DIMM module inserted correctly
    • Verify SW1 settings:
      SW1.2 = OFF
      SW1.1 = ON
    • Ensure correct steps followed in CORE Generator to generate required MIG IP core and modified UCF file carefully as per MIG IP. Ensure this runs properly (refer toUG416).
    • Download and run rdf0029.zip and xtp060.pdf (whichever version is appropriate for Silicon and Software version; i.e., xtp060_13.2_c.pdf and rdf0029_13.2_c.zip for 13.2 software and Production Silicon)
    • Read and follow guidelines in xtp060.pdf.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43748 Xilinx Boards and Kits - Debug Assistant N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
54022 How can I order TI USB Interface Adapter EVM from Texas Instruments? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40398 Virtex-6 FPGA ML605 Evaluation Kit - Board Debug Checklist N/A N/A
40399 Spartan-6 FPGA SP605 Evaluation Kit - Board Debug Checklist N/A N/A
AR# 40399
Date Created 02/01/2011
Last Updated 01/15/2016
Status Active
Type General Article
Boards & Kits
  • Spartan-6 FPGA SP605 Evaluation Kit