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AR# 40417

13.1 Timing Analysis - Why is my BRAM failing Component Switching Limits for Spartan-3A?

Description


I see the following failure in my timing report:



Component Switching Limit Checks: TS_DCM_clk = PERIOD TIMEGRP "DCM_clk" TS_CLK /?2.33333333 HIGH 50%;
--------------------------------------------------------------------------------
Slack: -0.215ns (period - min period limit)
Period: 4.285ns
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: TOP/CLKB
Logical resource: TOP/CLKB
Location pin: RAMB16_X1Y7.CLKB
Clock network: clkb



The data sheet for the Spartan-3A device outlines that the switching limit should be 280 MHz. Is this a bug?

Solution

Pease ignore the failure as this is a known issue in the tools and is scheduled bo fixed in the next major release of the software.
AR# 40417
Date Created 02/02/2011
Last Updated 04/11/2011
Status Active
Type General Article
Devices
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.0
  • ISE Design Suite - 13.1
  • Less