There is currently no support for simulation of the Soft Error Mitigation Controller. Functional and timing simulation of a design (including the controller) compiles, but the controller does not exit the initialization state. There is no support for partial reconfiguration when using the Soft Error Mitigation Controller. For further information on unsupported features and limitations, see Chapter 9 of the Soft Error Mitigation Controller User Guide (UG764).
The Soft Error Mitigation Controller has been verified using production Virtex-6 FPGA devices. Use of this core on Engineering Silicon (ES) devices is not supported due to a silicon errata item regarding "Configuration Readback". The core might not work at all on ES devices, and if it does, its operation might be unreliable.Therefore, this core must not be used in ES silicon for any purpose other than evaluation. If you are using this core on an ES device for evaluation and you encounter a problem, please obtain a production device. For more information, refer to the Virtex-6 FPGA CES Errata at: http://www.xilinx.com/support/documentation/virtex-6.htm#131587.
The following devices are supported by the core for this release:
(Xilinx Answer 39350) - Soft Error Mitigation - Timing Simulation Error:Warning: /X_FF RECOVERY Low VIOLATION ON RST WITH RESPECT TO CLK
(Xilinx Answer 40448)- Soft Error Mitigation Controller - Propagation of X's might occur during timing simulation
(Xilinx Answer 40991) -Soft Error Mitigation Controller - Correction by Replace not supported with EasyPath Devices
03/02/2011 - Added 40991
03/01/2011 - Initial Release