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AR# 40445 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Resolved issues in v2.3

Description

This article contains issues resolved in the Virtex-6 FPGA Integrated Block v2.3 Wrapper for PCI Express that are also listed in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

For other known and resolved issues that may not be in this list see (Xilinx Answer 45723)

Solution

Resolved Issues

  • Synplify script invoking Verilog files in VHDL project
    • CR 589321
    • Issue resolved where the Synplify script was invoking Verilog source files in a VHDL project.
  • BUFG added on TXOUTCLK to MMCM path
    • CR 579207
    • BUFG added to TXOUTCLK path to the MMCM to work around requirement of MMCM in same region as the PCI Express Integrated Block when the TXOUTCLK drives the MMCM input directly.
  • Core TxOutClk constraint added to UCF
    • CR 589216
    • Constraint added to TxOutClk BUFG output as sys_clk constraint was not propagated correctly by tools.
  • Virtex-6 GTX Transceiver Delay Aligner Errata Work-around
    • CR 585954
    • GTX transceiver settings have been updated to work around the Virtex-6 GTX Transceiver Delay Aligner Errata.
  • GTX Wrapper updated
    • CR 585171
    • The GTX Wrapper updated per latest recommendations for GTX Transceiver for PCI Express.
  • Default Reference Clock Frequency updated
    • CR 585171
    • The default reference clock frequency for Designs with Link Speed 5.0 Gb/s been changed from 250 MHz to 100 MHz.
  • PMA_RX_CFG attribute in GTX wrapper updated
    • CR 566981
    • The PMA_RX_CFG attribute in the GTX wrapper has been updated to be set based on Synchronous or Asynchronous clocking selected (Slot Clock selection).
  • Transaction Buffer Pipeline default setting for 8-lane Gen2 configuration
    • CR 572926
    • The default setting for Transaction Buffer Pipeline for 8-lane Gen2 configurations has been updated to "Buffer Write and Read"
  • INTERRUPT_PIN attribute update based on Legacy Interrupt option in GUI
    • CR 581046
    • Issue resolved where un-checking the Legacy Interrupt option was not updating the INTERRUPT_PIN attribute.

Revision History
01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723.
12/02/2011 - Minor update to fix format for Documentation Center viewing.
06/21/2011 - Fixed known issue bullet formatting. Removed issue related to x1G2 VHDL linking up. This configuration works fine and there are no issues.
03/29/2011 - Added Answer Record 41509
03/04/2011 - Added Answer Records 41051 and 41052
03/01/2011 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

Actions

AR# 40445
Date Created 02/04/2011
Last Updated 05/20/2012
Status Active
Type Release Notes
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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