For installation instructions, general CORE Generator tool known issues and design tools requirements, see the IP Release Notes Guide:
Do not use this version of the core for engineering sample (ES) silicon. The only supported version for ES silicon is v1.3 Rev 2. For more information, see (Xilinx Answer 34033).
This is the legacy TRN interface version of the core. Version 2.x of the core is for AXI4-Stream interfaces.
- ISE 13.1 software support
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-6 HXT
- Virtex-6 CXT
- Virtex-6 Lower Power
- QPro Virtex-6 Hi-Rel
- Core TxOutClk constraint added to UCF
- CR 589216
- Constraint added to TxOutClk BUFG output as sys_clk constraint was not propagated correctly by tools.
- Virtex-6 GTX Transceiver Delay Aligner Errata Workaround
- CR 585954
- GTX transceiver settings have been updated to work around the Virtex-6 GTX Transceiver Delay Aligner Errata.
- GTX Wrapper updated
- CR 585171
- The GTX Wrapper updated per latest recommendations for GTX Transceiver for PCI Express.
- Default Reference Clock Frequency updated
- CR 585171
- The default reference clock frequency for Designs with Link Speed 5.0 Gb/s been changed from 250 MHz t100 MHz.
- PMA_RX_CFG attribute in GTX wrapper updated
- CR 566981
- The PMA_RX_CFG attribute in the GTX wrapper has been updated to be set based on Synchronous or Asynchronous clocking selected (Slot Clock selection).
- Transaction Buffer Pipeline default setting for 8 lane Gen2 configuration
- CR 572926
- The default setting for Transaction Buffer Pipeline for 8 lane Gen2 configurations has been updated to "Buffer Write and Read"
- INTERRUPT_PIN attribute update based on Legacy Interrupt option in the GUI
- CR 581046
- Issue resolved where unchecking the Legacy Interrupt option was not updating the INTERRUPT_PIN attribute.
- trn_trem_n not connected in PIO_EP.vhd
- CR 577673
- Issue resolved where trn_trem_n was not connected ttrn_trem_n_int, in PIO_EP.vhd, causing this output to not be driven.
Note: CR 579207 is listed as resolved in the text readme that accompanies the core. This is a documentation mistake as this CR was not actually implemented since the GTX Delay Aligner work-around does not allow this use model.
- (Xilinx Answer 34009) - Virtex-6 FPGA ML605 Board - PCI Express link will not train on boards using ES silicon
- (Xilinx Answer 37784) - Virtex-6 FPGA Integrated Block Wrapper v2.2 and v1.7 for PCI Express - x8 Gen 2 Timing Closure
- (Xilinx Answer 38848) - Virtex-6 Integrated Block Wrapper v1.6 for PCI Express - Corrections for UG517
- (Xilinx Answer 41509) - 7 series and Virtex-6 Integrated Block for PCI Epxress - MSI-X Table Size field in Customization GUI should be entered as decimal number
- (Xilinx Answer 42346) - Virtex-6 FPGA Integrated Block Wrapper v1.7 for PCI Express - What is the PMA_RX_CFG setting for an asychronous link?
- (Xilinx Answer 43581) - Virtex-6 Integrated Block for PCI Express - Updated GTX attributes for v1.7 core version
12/02/2011 - Minor update to format for documentation center viewing.
08/11/2011 - Added 42346, 43851
03/30/2011 - Added 41509
03/04/2011 - Added 41051 and 41052.
03/01/2011 - Initial Release