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AR# 40452

MIG 7 Series v1.1 - Memory interface should not span both High Range (HR) and High Performance (HP) banks

Description

In MIG 7 Series v1.1, the bank selection page does not prevent the combination of High Range (HR) and High Performance (HP) banks in a memory interface.

This means an interface could be generated where Data and Address/Control are located in both HR and HP banks.

This combination would result in different I/O standards on the same memory interface bus.

MIG should prevent this combination.

Solution

To work around this GUI issue, ensure that the bank selection for a memory interface is contained within either High Range or High Performance banks. 

The MIG tool properly implements this bank selection rule starting in MIG 7 Series v1.2 (to be released with ISE Design Suite 13.2).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40452
Date Created 02/10/2011
Last Updated 08/12/2014
Status Active
Type General Article
Devices
  • Virtex-7
Tools
  • ISE Design Suite - 13.1
IP
  • MIG