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AR# 40466

Virtex-6 FPGA Integrated Block Wrapper v2.3 for PCI Express (AXI) - m_axis_rx_tstrb[7:0] only outputs 0x0F

Description

Known Issue: v2.3, v2.2, v2.1

When using the 64-bit interface, due to a mistake in the axi_basic_rx_pipeline.vhd file found in the generated core's source directory, the m_axis_rx_tstrb[7:0] output to the user will only output 0x0F. This is only a problem with the 64-bit VHDL wrapper. This is not a problem with the x8 GEN2 128-bit VHDL wrapper or any of the Verilog-HDL wrappers.

Solution


To fix this problem, edit the axi_basic_rx_pipeline.vhd found in the generated core's source directory to change the GENERATE statement starting on line 380. Modify the assignments to tstrb and tstrb_prev. Notice the change below is to change "11" to "1".



Change:



xhdl15 : IF (C_DATA_WIDTH = 64) GENERATE
-- 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
-- TSTRB has only two possible values here, 0xFF or 0x0F
tstrb <= x"FF" WHEN (TRN_RREM = "11") ELSE x"0F";
tstrb_prev <= x"FF" WHEN (trn_rrem_prev = "11" ) ELSE x"0F";
END GENERATE;


To:

xhdl15 : IF (C_DATA_WIDTH = 64) GENERATE
-- 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
-- TSTRB has only two possible values here, 0xFF or 0x0F
tstrb <= x"FF" WHEN (TRN_RREM = "1") ELSE x"0F";
tstrb_prev <= x"FF" WHEN (trn_rrem_prev = "1" ) ELSE x"0F";
END GENERATE;


Revision History
03/01/2011 - Initial Release
AR# 40466
Date Created 02/04/2011
Last Updated 02/25/2011
Status Active
Type ??????
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express