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AR# 40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions

Description

This Release Notes and Known Issues Answer Record is for the 7 series Integrated Block for PCI Express, first released in ISE Design Suite 13.1 and contains the following information:
  • General Information
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.

Additional documentation for this core can be found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express.htm

Solution

General Information

  • The ISE 14.5 design tool release contains the v1.9 core.
  • For 7 series Integrated Block for PCI Express v2.0 core release notes, see (Xilinx Answer 54643).
  • For 7 series FPGAs GTX/GTH transceivers known issues and answer record list, see (Xilinx Answer 37179).

New Features

  • ISE 14.5 design tool support.

Supported Devices

  • Virtex-7, Kintex-7, Artix-7, Zynq-7000
  • 7 series Integrated Block does not support targeting SSIT devices with the ISE tool flow. Customers wishing to target SSIT devices (1500T and 2000T) must use Vivado development environment.
  • See the product guide for specific device support within each family.

Note: For the previous versions "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Known Issues

This table correlates the core version to the first ISE design tools release version in which it was included.

Core Version
Vivado Tools Version
ISE Tools Version
v1.9 NA ISE 14.5
v1.8.1 2012.4.1 ISE 14.4.1
v1.8 2012.4 ISE 14.4
v1.7 2012.3 ISE 14.3
v1.6 2012.2 ISE 14.2
v1.5
 2012.1
ISE 14.1
v1.4
 2012.1
ISE 14.1
v1.3
 N/A
ISE 13.4
v1.2
 N/A
ISE 13.3
v1.1
 N/A
ISE 13.1

For 7-Series FPGA Errata, please check : http://www.xilinx.com/support/documentation/7_series_errata.htm

The following table provides known issues for the 7 series Integrated Block for PCI Express.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

 

Article Number
Article Title
Version Found
Version Resolved
(Xilinx Answer 55311) Downstream Memory Write transactions fail in VHDL example design simulation for the core generated with 128 bit interface width v1.9 Not Resolved Yet
(Xilinx Answer 54232) (ISE 14.4/ Vivado 2012.4) - How to generate the core for Artix-7 Production Silicon v1.8 v1.8.1
(Xilinx Answer 53740) (ISE 14.4 / Vivado 2012.4) - No Clock Output on TXOUTCLK at Cold Temperature v1.8 v1.9
(Xilinx Answer 53250) (Vivado 2012.4) - Setup timing violation on userclk1 v1.8 Not Resolved Yet
(Xilinx Answer 53251) (ISE 14.4) - Setup timing violations on paths between ../pcie_block_i (CPU) and [../bram36_dp_bl.bram36_tdp_bl (RAM)]/ ] / [../sdp_bl.ramb36_dp_bl.ram36_bl (RAM)] v1.8 Not Resolved Yet
(Xilinx Answer 53056) (ISE 14.3) ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd" does not exist v1.7 Not Resolved Yet
(Xilinx Answer 52968) (Vivado 2012.3) Simulation warning in Cadence IES "ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*})" v1.7 v1.8
(Xilinx Answer 52447) (Vivado 2012.3) userclk2 incorrectly constrained in XDC file when generating x8Gen2 core for KC705 board v1.7 v1.8
(Xilinx Answer 50683) (ISE 14.3/Vivado 2012.3) MSI Per Vector Masking Capability Support v1.7 Not Resolved Yet
(Xilinx Answer 52441) (ISE 14.3) Tandem PROM support for Kintex 410T devices v1.7 Not Resolved Yet
(Xilinx Answer 51448) 7 Series FPGA GTP Transceivers - RX Termination Use Modes v1.6 Not Resolved Yet
(Xilinx Answer 51135) The core does not link up on Z77(Ivy Bridge) platform v1.6 v1.9/v2.0
(Xilinx Answer 51381) UCF in the example design has a TIG constraint for 125MHz clock even for Gen1 mode v1.4 v1.7
(Xilinx Answer 51285) (Vivado 2012.2) - Does not link train with XCV72000T devices v1.6 v1.7
(Xilinx Answer 50692) (ISE 14.1/Vivado 2012.1) - The core may truncate some DLLPs/TLPs during the process of going into Recovery v1.4 Not Resolved Yet
(Xilinx Answer 50944) (ISE 14.2/Vivado 2012.2) - Tandem PCIe and Tandem PROM support v1.6 v1.7
(ISE 14.2/Vivado 2012.2) - VHDL simulation support for Root Port Configuration v1.6 Not Resolved Yet
(Xilinx Answer 50186)
 (Vivado 2012.1) - x8 Link Width not supported on Artix devices
v1.5
 v1.6
(Xilinx Answer 47969)
 (ISE 14.1) - Core generation for XC7V1500T and XC7V2000T devices
v1.4
v1.6
(Xilinx Answer 47907)
 (Vivado 2012.1) - VHDL Root Port Configuration Support
v1.4
 v1.6
(Xilinx Answer 47626)
 (ISE 14.1/Vivado 2012.1) -VHDL Simulation Support in Endpoint Configuration
v1.4
v2.0 (Use XSIM)
(Xilinx Answer 47627)
 (ISE 14.1) - Incorrect Completion Packets Generation for Interface Width 128-bit with Configuration Other than x8Gen2
v1.4
v1.5
(Xilinx Answer 47628)
 (ISE 14.1 / Vivado 2012.1) - Timing Violations in Certain IP Configurations
v1.4
Not Resolved Yet
(Xilinx Answer 47629)
 (Vivado 2012.1) - Core Configurations Other than x1Gen1 (64-bit) and x1Gen2 (64-bit) not Supported
v1.4
v1.5
(Xilinx Answer 47630)
 (Vivado 2012.1) - VHDL Support in Endpoint Configuration
v1.4
v1.5
(Xilinx Answer 47632)
 (Vivado 2012.1) - Root Port Configuration Support
v1.4
v1.5
(Xilinx Answer 47316)
 Enabling OOB Clock Mode
v1.3
v1.6
(Xilinx Answer 44732)
ISIM example script fails to compile when using VHDL
v1.2
v1.6
(Xilinx Answer 44682)
VHDL Flow Does Not Produce VHDL for MGT Wrapper Files
v1.2
Not Resolved Yet
(Xilinx Answer 44681)
Is Synplify supported?
v1.1
Verilog Support in v1.6
(Xilinx Answer 44643)
Signals cfg_pm_halt_l1, cfg_pm_force_state[1:0] seem to imply APSM L1 is supported
v1.2
v1.3
(Xilinx Answer 44625)
VHDL Simulation Results in "Failure: Rx Simulation Timeout"
v1.2
v1.3
(Xilinx Answer 44353)
How to target the Kintex-7 Integrated Block Wrapper to the KC705 boards
v1.1
v1.2
(Xilinx Answer 44351)
Blocks on left side may have unpredictable behavior when using ISE 13.2
v1.1
v1.2
(Xilinx Answer 42873)
Selectable Devices That Are Not Supported.
v1.1
v1.2
(Xilinx Answer 42830)
sys_reset_n does not have a pin location constraint.
v1.1
v1.2
(Xilinx Answer 43107)
Missing BRAM LOC constraints in UCF.
v1.1
v1.2
(Xilinx Answer 45541)
Pin to Pin Skew timing constraint failure targeting -2L
v1.1
v1.3
(Xilinx Answer 43949)
Link Training fails due to incorrect MGT attributes
v1.1
v1.1 Rev 2
(Xilinx Answer 40595)
x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate
v1.1
v1.1 Rev 1
(Xilinx Answer 41053)
Simulation link up takes too long
v1.1
v1.1 Rev 1
(Xilinx Answer 41271)
RECRC Check and Trim TLP Digest overlap.
v1.1
v1.1 Rev 1
(Xilinx Answer 45734)
MSI-X Table Size Field in Customization GUI Should Be Entered as Decimal Number
v1.1
v1.1 Rev 1
(Xilinx Answer 42838)
A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON
v1.1
v1.1 Rev 1



Revision History

04/03/2013 - Updated for ISE 14.5 Release
02/14/2013 - Added (Xilinx Answer 54232)
01/21/2013 - Added (Xilinx Answer 53740)
12/18/2012 - Updated for ISE 14.4/Vivado 2012.4 Release
11/26/2012 - Added (Xilinx Answer 53056)
11/20/2012 - Added (Xilinx Answer 52968)
10/03/2012 - Updated for ISE 14.3/Vivado 2012.3 Release
09/25/2012-  Added (Xilinx Answer 51448)
09/17/2012 - Added (Xilinx Answer 51135)
09/06/2012 - Added (Xilinx Answer 51381)
08/15/2012 - Added (Xilinx Answer 51285)
07/25/2012 - Updated for v1.6
05/31/2012- Added (Xilinx Answer 50186)
05/18/2012 - Added (Xilinx Answer 47969)
05/08/2012 - Updated for ISE 14.1 and Vivado 2012.1 design tools and v1.4
05/01/2012 - Added (Xilinx Answer 47316)
03/06/2012 - Updated title for (Xilinx Answer 44681)
01/18/2012 - Updated for ISE 13.4 Design Suite and v1.3.
10/21/2011 - Updated for ISE 13.3 Design Suite and v1.2
10/06/2011 - Added (Xilinx Answer 44353) and (Xilinx Answer 44351)
09/26/2011 - Added (Xilinx Answer 43347) and (Xilinx Answer 43423)
09/07/2011 - Added (Xilinx Answer 43949)
08/12/2011 - Changed known issues to table format
07/14/2011 - Added (Xilinx Answer 43107)
07/06/2011 - Updated for ISE 13.2 Design Suite and v1.1 Rev 1
03/29/2011 - Added (Xilinx Answer 41509)
03/28/2011 - Added (Xilinx Answer 41271)
03/03/2011 - Added (Xilinx Answer 41053)
03/01/2011 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51901 Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record N/A N/A
45382 Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
51900 Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
47316 7 Series Integrated Block for PCI Express v1.3 - Enabling OOB Clock Mode N/A N/A
45734 7 Series Integrated Block for PCI Express - MSI-X Table Size field in customization GUI should be entered as decimal number N/A N/A
45541 7 Series Integrated Block for PCI Express - Pin to Pin Skew timing constraint failure when targeting -2L speed grade N/A N/A
44682 7 Series Integrated Block for PCI Express - VHDL flow does not produce VHDL for MGT wrapper files N/A N/A
44681 7 Series Integrated Block for PCI Express - Is Synplify synthesis supported N/A N/A
44643 7 Series Integrated Block for PCI Express - Signals cfg_pm_halt_l1, cfg_pm_force_state[1:0] seem to imply APSM L1 is supported N/A N/A
44625 7 Series Integrated Block for PCI Express - VHDL simulation results in "Failure: Rx Simulation Timeout" N/A N/A
44353 7 Series Integrated Block for PCI Express - How to Target the Kintex-7 Integrated Block Wrapper to the KC705 Boards N/A N/A
43107 7 Series Integrated Block Wrapper for PCI Express - Missing block RAM LOC constraints in UCF N/A N/A
42838 7 Series Integrated Block for PCI Express - A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON N/A N/A
42164 7 Series Integrated Block Wrapper v1.1 for PCI Express - Component Switching Limit Error Occurs with x8 gen2 Core when a Virtex-7 -1 Speed Grade Is Targeted N/A N/A
41271 7 Series Integrated Block for PCI Express - RECRC Check and Trim TLP Digest overlap N/A N/A
41053 7 Series Integrated Block for PCI Express - Simulation link up takes too long N/A N/A
40595 7 Series Integrated Block for PCI Express - x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate N/A N/A
42873 7 Series Integrated Block for PCI Express - Selectable Devices That Are Not Supported N/A N/A
47907 7 Series Integrated Block for PCI Express v1.5 (Vivado 2012.1) - VHDL Root Port Configuration Support N/A N/A
47862 7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - Download, Installation and Usage Instructions N/A N/A
47632 7 Series Integrated Block for PCI Express v1.4 (Vivado 2012.1) - Root Port Configuration Support N/A N/A
47630 7 Series Integrated Block for PCI Express v1.4 (Vivado 2012.1) - VHDL Support in Endpoint Configuration N/A N/A
47629 7 Series Integrated Block for PCI Express v1.4 (Vivado 2012.1) - Core configurations other than x1Gen1 (64-bit) and x1Gen2 (64-bit) are not supported N/A N/A
47628 7 Series Integrated Block for PCI Express v1.4 (ISE 14.1 / Vivado 2012.1) - Timing violations in certain IP configurations N/A N/A
47627 7 Series Integrated Block for PCI Express v1.4 (ISE 14.1) - Incorrect completion packets generation for interface width 128-bit with configuration other than x8Gen2 N/A N/A
47626 7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - VHDL Simulation Support for Endpoint Configuration N/A N/A
47969 7 Series Integrated Block for PCI Express v1.4 (ISE 14.1) - Core generation for XC7V1500T and XC7V2000T devices N/A N/A
51285 7 Series Integrated Block Wrapper for PCI Express v1.6 (Vivado 2012.2) - Does not link train with XCV72000T devices N/A N/A
51381 7 Series Integrated Block for PCI Express v1.4 - UCF in the example design has a TIG constraint for 125 MHz clock even for Gen1 mode N/A N/A
52447 7 Series Integrated Block for PCI Express - v1.7 userclk2 incorrectly constrained in XDC file when generating x8Gen2 core N/A N/A
52968 7 Series Integrated Block for PCI Express v1.7 (Vivado 2012.3) - Simulation warning in Cadence IES "ncelab: *W,?CSINFI: implicit wire has no fanin ({*Name Protected*})" N/A N/A
53250 7 Series Integrated Block for PCI Express - v1.8 (Vivado 2012.4) - Setup timing violation on userclk1 N/A N/A
53251 7 Series Integrated Block for PCI Express - v1.8 (ISE 14.4) - Setup timing violations on paths between ../pcie_block_i (CPU) and [../bram36_dp_bl.bram36_tdp_bl (RAM)]/ ] / [../sdp_bl.ramb36_dp_bl.ram36_bl (RAM)] N/A N/A
53740 Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature N/A N/A
54232 7 Series Integrated Block Wrapper for PCI Express v1.8 (ISE 14.4/2012.4) - How to generate the core for Artix-7 Production Silicon? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40595 7 Series Integrated Block for PCI Express - x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate N/A N/A
41271 7 Series Integrated Block for PCI Express - RECRC Check and Trim TLP Digest overlap N/A N/A
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A

Actions

AR# 40469
Date Created 02/11/2011
Last Updated 04/02/2013
Status Active
Type Release Notes
IP
  • 7 Series Integrated Block for PCI Express (PCIe)
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