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AR# 4048

M1.4 CPLD Hitop - Incorrect logic generated.

Description

Customer doing an VHDL design with the following equations:

RST <= not RST_N;

RST_N <= reset_in_n and watchdog_rst_n;

In the functional simulation, the logic is correct.

After running the design through the core tools the fitter report shows the equation to be:

/RST = reset_in_n * watchdog_rst_n

/RST_N = reset_in_n * watchdog_rst_n

The signal is incorrect and the customer verified it by doing a timing simulation. It appears that the fitter is inverting the signal twice.

Please see the readme.txt for command lines used.

Solution

This problem has been corrected in the latest CPLD patch available
on the Xilinx support website:

http://support.xilinx.com/support/techsup/sw_updates/
AR# 4048
Date Created 06/09/1998
Last Updated 03/29/2000
Status Archive
Type General Article