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AR# 40486

13.1 ChipScope Pro IBERT - Generation fails at NGDBuild with "ERROR:NgdBuild:604" and "ERROR:NgdBuild:456"


When I generate an IBERT core targeting a Virtex-6 LXT and specify the ML605 board, core generation fails and the followingwarning messages occur:

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_U_TO_D = FROM U_CLK TO D_CLK TIG ;> [ibert_core.ucf(36)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'U_CLK'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;> [ibert_core.ucf(37)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'J_CLK'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;> [ibert_core.ucf(38)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'J_CLK'.

INFO:ConstraintSystem - The Period constraint <NET "ibert_sysclock" PERIOD = 200.0 MHz;> [ibert_core.ucf(83)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method.

WARNING:NgdBuild:1012 - The constraint <INST /example_chipscope_ibert/EXPANDED/example_chipscope_ibert/U_SYSCLOCK_IBUFDS
IOSTANDARD = "DEFAULT"> is overridden on the design object U_SYSCLOCK_IBUFDS by the constraint <INST "U_SYSCLOCK_IBUFDS" IOSTANDARD = LVDS_25;> [ibert_core.ucf(80)].

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'U_ICON' with type 'chipscope_icon_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'chipscope_icon_1' is not supported in target 'virtex6'.
ERROR:NgdBuild:456 - logical net 'CONTROL0<3>' has both active and tristate drivers...
Active driver(s) of net 'CONTROL0<3>':
'Q' pin on block
Tristate driver(s) of net 'CONTROL0<3>':
'CONTROL0<3>' pin on block 'U_ICON' ( chipscope_icon_1 )

How do I work around this issue?


This issue occurs when youchoose the ml605 bank113fmchpc board from the Board Settings drop-down.

This issue is scheduled to be resolved in the ChipScope Pro 13.2 tool. In the meantime, you can work around this issue using the following two possibilities:

Modify the component names and rerun implementation manually

  1. Uncheck the "Generate Bitstream" checkbox when selecting IBERT options.
  2. Modify the example_<component_name>.vhd/example_<component_name>.v file in "<project_name>/tmp/_cg/<component_name>/example_design" folder with the following changes - Change the icon instantiation name from "chipscope_icon_2" to "chipscope_icon".
  3. Change to "<project_name>/tmp/_cg/<component_name>/implement" directory and run implement. sh or implement.bat

Manually set up the IBERT core rather than choosing the board settings

  1. System Clock Settings:
    • Use External Clock Source
    • Frequency = 200 MHz
    • Pin Location = J9
    • Pin input Standard = LVDS 25
  2. Line Rate Settings:
    • Number of Protocols = 1
    • Name Protocol = fmc_hpc
    • Max Rate =5.0
    • Data Width= 20
    • Refclk = 250 MHz
    • GTX Count = 5
  3. Assign GTXs to a protocol:
    • X0Y4 = fmc hpc/5.0 Gbps
    • X0Y5 = fmc hpc /5.0 Gbps
    • X0Y6 = fmc hpc /5.0 Gbps
    • X0Y7 = fmc hpc /5.0 Gbps
    • X0Y11 = fmc hpc /5.0 Gbps
  4. Set Refclk Source:
    • All set to Q2-Refclk0

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40485 13.x ChipScope Pro - Known Issues for the ChipScope Pro 13.x Software N/A N/A
AR# 40486
Date Created 02/10/2011
Last Updated 01/02/2013
Status Active
Type General Article
  • ChipScope Pro - 13.1