Block RAM used in the 9K mode (RAMB8BWER) can fail to initialize user specified data or default values (all zeros) during configuration inall Spartan-6devices.
Based on the selected IP Parameters, the cores listed below might use a block RAM in 9K mode and need to use the default or pre-initialized values.
If you are using one of the IP listed below, you should review the MAP report to see if your design is using the RAMB8BWER. As of ISE Design Suite 13.1, designs containing 9K block RAM will see a physical DRC warning in MAP and in BitGen.
If you see this warning and are using one of the IP listed below, there is a patch available for the MAP tool which retargets all 9K block RAMs to 18K block RAMs (RAMB8BWER to RAMB16BWER).
To obtain this patch, please contact Xilinx Technical Support,or see (Xilinx Answer 39999) for more details.
Xilinx is continuing to investigate this issue, and will provide updates when other ways to work around this issue are available.
If your design does contain a RAMB8BWER, see the Spartan-6 Errata (including EN148) and (Xilinx Answer 39999) for more details on the Spartan-6 9k block RAM initialization issue.
| System Logic | ||
| Block Memory Generator | ||
| FIFO Generator -(Xilinx Answer 40672) | ||
| DSP IP Horizontal | ||
| CORDIC | ||
| Direct Digital Synthesizer Compiler (DDS Compiler) | ||
| DUC/DDC Compiler | ||
| Fast Fourier Transform (FFT) | ||
| FIR Compiler | ||
| Multiplier | ||
| DSP IP Digital Communications | ||
| Digital Pre-Distortion (DPD) | ||
| DVB S2 FEC Encoder | ||
| Interleaver/De-Interleaver | ||
| LTE DL Channel Encoder | ||
| Reed Solomon Decoder | ||
| Reed Solomon Encoder | ||
| Viterbi Decoder | ||
| Multimedia Video And Imaging | ||
| Color Filter Array Interpolation | ||
| Defective Pixel Correction | ||
| Gamma Correction | ||
| Image Edge Enhancement | ||
| Image Statistics Engine | ||
| Video Object Segmentation | ||
| Video On Screen Display | ||
| Video Scaler | ||
| Triple-Rate SDI | ||
| Wireless | ||
| CPRI | ||
| OBSAI | ||
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 39999 | Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46792 | Spartan-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems | N/A | N/A |
| 40660 | LogiCORE IP Digital Pre-Distortion (DPD) v4.0 - How is the IP affected by the Spartan-6 9K Block RAM Issue? | N/A | N/A |
| 40542 | LogiCORE IP OBSAI v 4.1 - How is the IP affected by the Spartan-6 9K block RAM issue? | N/A | N/A |
| 40541 | Logicore CPRI v 3.2 - How is the IP affected by the Spartan-6 PK BRAM Issue? | N/A | N/A |
| 39999 | Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support | N/A | N/A |