Solution

General Information
For full details on the required I/O clocks, PLL clocking structure (see the "Clocking Architecture" figure), and the guidelines for changing the input clock frequency while ensuring jitter is minimized, see the "Clocking Architecture" section in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).

The MIG tool (starting with MIG v1.2) allows users to input the Memory Clock Period and then lists available Input Clock Periods that follow the supported clocking guidelines. Based on these two clock periods selections, the generated MIG core appropriately sets the PLL parameters.

Input Clock Guidelines

• PLL Guidelines
• CLKFBOUT_MULT_F (M) must be between 1 and 16 inclusive.
• DIVCLK_DIVIDE (D, Input Divider) can be any value supported by the PLLE2 parameter.
• CLKOUT_DIVIDE (O, Output Divider) must be 2 for 400 MHz and up operation and 4 for below 400 MHz operation.
• The above settings must ensure the minimum PLL VCO frequency (FVCOMIN) is met. For specifications, see the appropriate DC and Switching Characteristics Data Sheet. The 7 Series FPGAs Clocking Resources User Guide (UG472) includes the equation for calculating FVCO.
• The relationship between the input period and the memory period is InputPeriod = (MemoryPeriod*M)/(D*D1).

• The clock input (sys_clk) can now be input on any CCIO in the column where the memory interface is located; this includes CCIO in banks that do not contain the memory interface, but must be in the same column as the memory interface. The PLL must be located in the bank containing the clock sent to the memory. To route the input clock to the memory interface PLL, the CMT backbone must be used. With the MIG implementation, one spare interconnect on the backbone is available that can be used for this purpose.

• MIG 1.4, released with ISE Design Suite 13.4, allows this input clocking set-up and properly drives the CMT backbone.
• For DDR3 interfaces that have the memory system input clock (sys_clk) placed on CCIO pins within one of the memory banks, MIG assigns the DIFF_SSTL15 I/O standard (VCCO = 1.5V) to the CCIO pins. Since the same differential input receiver is used for both DIFF_SSTL15 and LVDS inputs, an LVDS clock source may be connected directly to the DIFF_SSTL15 CCIO pins. See below note for conditions.
• It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria must be met:
1. The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value). Note: This mayrequiremanually changing DIFF_TERM parameter located in the top-level module or setting this in the UCF.
2. The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet.
3. The differential signals at the input pins meet the VIDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific device family data sheet.

One way to accomplish the above criteria is to use an external circuit that both AC-couples and DC-biases the input signals. The below figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input. RDIFF provides the 100ohm differential receiver termination because the internal DIFF_TERM is set to FALSE. To maximize the input noise margin, all RBIAS resistors should be the same value, essentially creating a VICM level of VCCO/2. Resistors in the 10k-100K ohm range are recommended. The typical values for the AC coupling capacitors CAC are in the range of 100 nF. All components should be placed physically close to the FPGA inputs.

NOTE: The last set of guidelines on differential LVDS inputs will be added within the LVDS and LVDS_25 (Low Voltage Differential Signaling) section of the 7 Series SelectIO Resources User Guide (UG471) in the next release of the document.

NOTE: These guidelines are irrespective of Package, Column (HR/HP), or I/O Voltage.

Sharing sys_clk Between Controllers
As noted in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586), MIG 7 Series FPGA designs require sys_clk to be in the same I/O bank column as the memory interface to minimize jitter.

• Interfaces Spanning I/O Columns
  • A single sys_clk input cannot drive memory interfaces spanning multiple I/O columns. The input clock input must be in the same column as the memory interface in order to drive the PLL using the CMT Backbone, which minimizes jitter.
• Interfaces in Single I/O Column
  • If the memory interfaces are entirely contained within the same I/O column, a common sys_clk can be shared among the interfaces. The sys_clk can be input on any CCIO in the column where the memory interfaces are located. This includes CCIO in banks that do not contain the memory interfaces, but must be in the same column as the memory interfaces.

Information on Sharing BUFG Clock (phy_clk)
The MIG 7 Series DDR3 design includes an MMCM which outputs the phy_clk on a BUFG route. It is NOT possible to share this clock amongst multiple controllers to synchronize the user interfaces. This is not allowed because the timing from the fabric logic to the PHY Control Block must be controlled. This is not possible when the clock is shared amongst multiple controllers. The only option for synchronizing user interfaces amongst multiple controllers is to create an asynchronous FIFO for clock domain transfer.

Information on Sync_Pulse
The MIG 7 Series DDR3/DDR2 design includes one PLL that generates the necessary design clocks.One of these outputs is the "sync_pulse." The sync pulse clock is 1/16 of the mem_refclk frequency and must have a duty cycle distortion of 1/16 or 6.25%. This clock is distributed across the low skew clock backbone and keeps all PHASER_IN/_OUT and PHY_Control blocks in sync with each other. The signal is sampled by the mem_refclk in both the PHASER_INs/_OUTs and PHY_Control blocks. The phase, frequency, and Duty Cycle of the sync_pulse is chosen to provide the greatest setup and hold margin across PVT.

Revision History
06/28/12 - Added information on sharing phy_clk
06/27/12 - Added additional information on Sync Pulse
06/05/12 - Added information on differential LVDS clock inputs
03/20/12 - Added information on sys_clk I/O standard
03/06/12 - Added information on Sync Pulse
02/22/12 - Modified Interfaces Spanning I/O Columns section
01/31/12 - Combined all clocking information in this Answer Record (obsolete Answer Record 41587)
11/30/11 - Updated to include latest clocking guidelines and tool updates
08/15/11 - Updated CLKFBOUT_MULT_F (M) Guidelines
05/11/11 - Included updated PLL settings
05/24/11 - Included VCO information