The 7 Series FPGA MIG DDR2/DDR3 design has two clock inputs, the reference clock and the system clock.
The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks that are used to clock the internal logic, the frequency reference clocks to the phasers, and a synchronization pulse required for keeping PHY control blocks synchronized in multi-I/O bank implementations.
This answer record details the MIG 7 series FPGA clocking guidelines.
Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
The Xilinx MIG Solution Center is available to address all questions related to MIG.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For full details on the required I/O clocks, PLL clocking structure (see the "Clocking Architecture" figure), and the guidelines for changing the input clock frequency while ensuring jitter is minimized, see the "Clocking Architecture" section in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
The MIG tool (starting with MIG v1.2) allows users to input the Memory Clock Period and then lists available Input Clock Periods that follow the supported clocking guidelines.
Based on these two clock periods selections, the generated MIG core appropriately sets the PLL parameters.
Input Clock Guidelines
The clock input (sys_clk) can now be input on any CCIO in the column where the memory interface is located.
This includes CCIO in banks that do not contain the memory interface, but must be in the same column as the memory interface.
The PLL must be located in the bank containing the clock sent to the memory.
To route the input clock to the memory interface PLL, the CMT backbone must be used.
With the MIG implementation, one spare interconnect on the backbone is available that can be used for this purpose.
One way to accomplish the above criteria is to use an external circuit that both AC-couples and DC-biases the input signals.
The below figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input.
RDIFF provides the 100ohm differential receiver termination because the internal DIFF_TERM is set to FALSE.
To maximize the input noise margin, all RBIAS resistors should be the same value, essentially creating a VICM level of VCCO/2.
Resistors in the 10k-100K ohm range are recommended.
The typical values for the AC coupling capacitors CAC are in the range of 100 nF.
All components should be placed physically close to the FPGA inputs.
1) The last set of guidelines on differential LVDS inputs will be added within the LVDS and LVDS_25 (Low Voltage Differential Signaling) section of the 7 Series SelectIO Resources User Guide (UG471) in the next release of the document.
2) These guidelines are irrespective of Package, Column (HR/HP), or I/O Voltage.
Sharing sys_clk Between Controllers
As noted in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586), MIG 7 Series FPGA designs require sys_clk to be in the same I/O bank column as the memory interface to minimize jitter.
In certain designs due to clock source limitations, users would choose the no_buffer option in the MIG GUI and intend to drive system clock from different possible sources specified below
It is not possible to drive system clock from an IBUFDS_GTE2 as it does not satisfy the MIG requirement of routing the system clock on CLOCK_DEDICATED_ROUTE BACKBONE.
2. From a PLL/MMCM located in a different column
You cannot drive sys_clk_i from a PLL/MMCM that sits in different column to the MIG interface. Even with the no buffer option it is required that the system clock be driven from the same column as that of MIG by instantiating the buffer and providing necessary clock constraints.
Choosing the no buffer option in the MIG GUI means that the user will take care of buffer instantiation and system clock location at a later point in time, but MIG clocking rules should always be satisfied.
3. Sharing MMCM in multiple controller configurations -Information on Sharing BUFG Clock (phy_clk)
The MIG 7 Series DDR3 design includes an MMCM which outputs the phy_clk on a BUFG route.
It is NOT possible to share this clock amongst multiple controllers to synchronize the user interfaces.
This is not allowed because the timing from the fabric logic to the PHY Control Block must be controlled.
This is not possible when the clock is shared amongst multiple controllers.
The only option for synchronizing user interfaces amongst multiple controllers is to create an asynchronous FIFO for clock domain transfer.
For all of the three possible combinations Vivado might not generate an error or warning, but they do not come under supported clocking topology. Using them might not give you consistent and reliable results across PVTs.
|04/20/15||Added sharing clock for multiple SLRs|
|09/30/13||Added link to 53249|
|06/28/12||Added information on sharing phy_clk|
|06/27/12||Added additional information on Sync Pulse|
|06/05/12||Added information on differential LVDS clock inputs|
|03/20/12||Added information on sys_clk I/O standard|
|03/06/12||Added information on Sync Pulse|
|02/22/12||Modified Interfaces Spanning I/O Columns section|
|01/31/12||Combined all clocking information in this Answer Record (obsolete Answer Record 41587)|
|11/30/11||Updated to include latest clocking guidelines and tool updates|
|08/15/11||Updated CLKFBOUT_MULT_F (M) Guidelines|
|05/11/11||Included updated PLL settings|
|05/24/11||Included VCO information|