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AR# 40631 LogiCORE IP XAUI v10.1 - Release Notes and Known Issues for ISE Design Suite 13.1/13.2/13.3

Description

This Answer Record contains the Release Notes for the LogiCORE IP XAUI v10.1 Core, which was first released in the ISE Design Suite 13.1,andincludes the following:
  • New Features
  • Supported Devices
  • Bug Fixes
  • Known Issues
For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide. For LogiCORE IPXAUI Frequently Asked Questions (FAQ), see (Xilinx Answer 33596).

Solution

New Features

  • 13.1/13.2/13.3 ISE Design Suite Support

Supported Devices

  • Kintex-7 XC
  • Virtex-7 XC
  • Spartan-6 XQ LX/LXT
  • Virtex-5 XQ LXT/FXT/SXT
  • Virtex-6 XQ LXT/SXT
  • Spartan-6 XC LXT
  • Virtex-4 XC FX
  • Virtex-5 XC LXT/FXT/SXT/TXT
  • Virtex-6 XC CXT/LXT/HXT/SXT
  • Virtex-6L XC LXTL/SXTL

Note: For a complete part and package support list, please check Xilinx CORE Generator GUI under 'Supported Families' for XAUI v10.1.

Resolved Issues

Known Issues

  • (Xilinx Answer 40897) - LogiCORE IP - Xs are seen in ModelSim 6.6c functional or timing simulation
  • (Xilinx Answer 35241) -LogiCORE IP XAUI v9.2 - Timeout is seen in some Virtex-5 FPGA Example Design Timing Simulation
  • (Xilinx Answer 24678) - Virtex-4 FPGA GT11 SmartModel Simulation - TX serial output skewed in SimPrims Timing Simulation
  • (Xilinx Answer 42673) - LogiCORE IP XAUI v10.1, 7-Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2/13.3
  • (Xilinx Answer 42850) - RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in bitgenwhen targeting Virtex-7 or Kintex-7 devices
  • (Xilinx Answer 42842) - 7-Series GTX Transceiver - PLLREFCLK selection change causing simulation issue in ISEDesign Suite 13.1
  • (Xilinx Answer 44392) - LogiCORE IP XAUI v10.1, Kintex-7/Virtex-7 - GTRXRESET pin must be asserted until the PLL has locked
  • (Xilinx Answer 43482) - 7-Series GTX Transceiver Reset Requirements Upon Configuration
  • (Xilinx Answer 44858) LogiCORE IP XAUI v10.1 - GTn_RXCDRRESET and GTn_RXBUFRESET port connection changes in the block wrapper for 7-series devices in ISE Design Suite 13.2/13.3
  • (Xilinx Answer 44860) LogiCORE IP XAUI v10.1 - Required changes to implement the core on 7-Series IES devices

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
42673 LogiCORE IP XAUI v10.1, 7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2/13.3 Software N/A N/A
42850 RXAUI v2.1 and XAUI v10.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices N/A N/A

Actions

AR# 40631
Date Created 02/25/2011
Last Updated 05/20/2012
Status Active
Type Release Notes
IP
  • XAUI
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