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AR# 40634

Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Answer Record contains the Release Notes for the Virtex-6 FPGA LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v2.1, which was released in ISE DesignSuite 13.1, andincludes the following:

  • General Information
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

General Information

  • Supports automatic generation of HDL wrapper files for the Virtex-6 FPGA Tri-Mode Ethernet MAC
  • Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII, and 1000Base-X PCS/PMA configurations are supported)
  • Provides a FIFO-based example design
  • Provides a demonstration testbench for the selected configuration
  • (Xilinx Answer 33593) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Frequently Asked Questions (FAQ)

New Features

  • ISE 13.1 software support
  • Support for AXI4-Lite
  • Support for AXI4-Stream
  • All new memory mapped interface
  • Optional built-in statistics counters
  • New example design
  • 2 Gbps and 2.5 Gbps not supported

Supported Devices

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT

Resolved Issues

Known Issues Resolved in v2.1rev1

  • (Xilinx Answer 42663) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 (AXI) - Incorrect values read from statistics registers
  • (Xilinx Answer 42666) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 (AXI) - Ability register returns incorrect value

Known Issues in v2.1 and v2.1rev1

  • 2 Gbps and 2.5 Gbps 1000BASE-X not supported in this release
  • (Xilinx Answer 39960 Virtex-6 FPGA Embedded Tri-mode Ethernet MAC - Synopsys VCS back-annotated timing simulations time out
  • (Xilinx Answer 40028) LogiCORE IP Tri-Mode Ethernet MAC and Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 and later - Meeting GMII and RGMII setup and hold times when targeting Virtex-6 FPGAs
  • (Xilnx Answer 40314) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 (AXI) - 1000BASE-X functional simulation does not complete
  • (Xilinx Answer 43338) Virtex-4/Virtex-5/Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Configured for MII, GMII, or RGMII operation at 10 Mbps, MDIO transactions errors can occur

Download Rev1 Update

To get the Rev1 update with the resolved issues described above, apply the following patch to the Xilinx ISE 13.1 software installation: http://www.xilinx.com/txpatches/pub/swhelp/ise13_updates/ar40634_v6_emac_v2_1_rev1.zip.

Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE 13.1 software installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

After installing the patch, regenerate the Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v2.1 in the 13.1 CORE Generator tool. For further information on finding the Xilinx install and using environment variables, see (Xilinx Answer 11630).

Note: You might need system administrator privileges to install the patch if you do not have write permissions to the Xilinx installationdirectory.

Linked Answer Records

Child Answer Records

AR# 40634
Date Created 02/18/2011
Last Updated 05/20/2012
Status Active
Type Release Notes
IP
  • Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper