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AR# 40638

SPI-4.2 v10.4 - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) v10.4 Core (released in ISE Design Suite 13.1), and contains the following information:

  • New Features
  • Supported Devices
  • Resolved Issues
  • General Information
  • Known Issues

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features
  • ISE 13.1 software support

Supported Devices

  • Virtex-4, Virtex-5, Virtex-6, Virtex-6L
Resolved Issues
  • ERROR:ConstraintSystem:58 received when running NGDBuild on SPI-4.2 v10.3 example design in ISE 13.1
    • CR 586622
  • ERROR:NgdBuild:488 received when implementing a Verilog design targeting Virtex-4 in ISE 13.1
    • CR 585289
  • (Xilinx Answer 35270) - SPI-4.2 & SPI-4.2 Lite - Documentation does not describe behavior when partial credit is written
  • (Xilinx Answer 41710) - SPI-4.2 v10.3 and earlier - Dynamic Phase Alignment might fail when using "Sink DPA Clock Adjust" and targeting a Virtex-6 FPGA
General Information
  • (Xilinx Answer 37917) LogiCORE IP SPI-4.2 - Input Clocking requirement for source reference clock (SysClk)
  • Performance of Virtex-6 Source core is as follows:
  • (Xilinx Answer 32917) Virtex-6 FPGA change to HIGH_PERFORMANCE_MODE attribute for IODELAYE1 elements in UCF
  • If you are using multiple SPI-4.2 Cores in a single device, you must generate the core with a unique component name for each instance. See the Multiple Core Instantiation section under the Special Design Considerations chapter of the SPI-4.2 User Guide.
  • (Xilinx Answer 15500) How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM?
  • (Xilinx Answer 20017) Which I/O Standards are supported for the SPI-4.2 Core?
  • (Xilinx Answer 32942) Changing static configuration signals in-circuit
  • Sink DPA Clock Adjustment option for Global Clocking Mode is not supported for Virtex-6 devices
Known issues
  • (Xilinx Answer 40823) - SPI-4.2 - Updated Sink Core performance and MMCM settings for using Global Clocking on Virtex-6 devices
  • (Xilinx Answer 41130) - SPI-4.2 - Updated Source Core MMCM settings for using Global Clocking at 1G on Virtex-6 devices
  • (Xilinx Answer 39106) - SPI-4.2 Spartan-6 Device Support has been removed
  • (Xilinx Answer 40178) - SPI-4.2 v10.4 and v11.1 - DPA diagnostic port SnkDPARamValid does not assert correctly for Virtex-6, Virtex-7 and Kintex-7 devices
  • (Xilinx Answer 40829) - SPI-4.2 v10.4 - "ERROR:NgdBuild:604..." seen when using Synplify and targeting a Virtex-6 device
  • (Xilinx Answer 41711) - SPI-4.2 v10.4 and v11.1 - Dynamic Phase Alignment might fail when using "Sink DPA Clock Adjust" and targeting a Virtex-6 FPGA
Constraints and Implementation Issues
  • (Xilinx Answer 20000) - When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21439) - When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21320) - When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear
  • (Xilinx Answer 21363) - PAR has problems placing components or completely routing the SPI4.2 design in my design
  • (Xilinx Answer 20280) - Placement failures occur in PAR when the SPI-4.2 FIFO Status Signals' I/O Standard is set to LVTTL I/O
  • (Xilinx Answer 20040) - Timing Analyzer (TRCE) reports "0 items analyzed"
  • (Xilinx Answer 20319) - When running implementation, undefined I/O (single-ended) defaults to LVCMOS causes WARNINGS in NGDBuild
General Simulation Issues
  • (Xilinx Answer 24026) - When I run simulation on SPI-4.2 design, Locked_RDClk (from RDClk DCM) might get de-asserted after PhaseAlignRequest
  • (Xilinx Answer 21319) - When I run timing simulation on an SPI-4.2 design example, several "TDat Error: Data Mismatch" messages are reported
  • (Xilinx Answer 21321) - Timing simulation error: # ** Error: */X_ISERDES SETUP Low VIOLATION ON D WITH RESPECT TO CLK;
  • (Xilinx Answer 21322) - When I run timing simulation on a SPI4.2 design, several SETUP, HOLD, and RECOVERY violations occur
  • (Xilinx Answer 20030) - When I simulate an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation
  • (Xilinx Answer 15578) - When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
42882 SPI-4.2 v10.4 - Timing errors encountered when using the 128-bit client interface N/A N/A
AR# 40638
Date Created 02/23/2011
Last Updated 05/20/2012
Status Active
Type Release Notes
IP
  • SPI-4 Phase 2 Interface Solutions