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AR# 40653

12.2 EDK, MPMC - Reduced drive output enable C_MEM_REDUCED_DRV not set correctly

Description

When I set the MPMC parameter C_MEM_REDUCED_DRV to "1" in Virtex-6 FPGA, MPMC sets DDR3 mode register MR1[5,1] to "00". In Spartan-6 FPGA, the opposite setting is set. Which is correct?

According to the MPMC data sheet, the description of C_MEM_REDUCED_DRV for DDR3 is as follows:

0 = RZQ/6
1 = RZQ/7
2 = Reserved
3 = Reserved

Solution

In Virtex-6 FPGA, setting C_MEM_REDUCED_DRV = 1 will correctly produce a reduced drive setting of RZQ/6. However, the data sheet and MPMC GUI labels are incorrect. It will be fixed to:

0 = RZQ/7
1 = RZQ/6
2 = Reserved
3 = Reserved

In Spartan-6 FPGA MPMC, the behavior of C_MEM_REDUCED_DRV is inverted from its normal meaning. To work around, invert the parameter until this issue is fixed. These issues are scheduled to be fixed in EDK 13.2.

AR# 40653
Date Created 02/18/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 LX
  • Virtex-6 LXT
Tools
  • EDK - 11.2
  • EDK - 11.3
  • EDK - 11.4
  • More
  • EDK - 11.5
  • EDK - 12.1
  • EDK - 12.2
  • EDK - 12.3
  • EDK - 12.4
  • EDK - 13
  • EDK - 13.1
  • Less
IP
  • Multi-Port Memory Controller (MPMC)