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AR# 40741

MIG v3.61-v3.7 Virtex-6 QDRII+ - "WARNING:PhysDesignRules:2282 - Invalid configuration (incorrect pin connections and/or modes) on block..."


When the MIG v3.61 V6 QDRII design is generated with all of the default options, it causes a BitGen DRC warning message in ISE Design Suite 12.4.

The ODELAY_TYPE=FIXED attribute for each IODELAYE1 being used in the MIG design causes the following warning during BitGen:

WARNING:PhysDesignRules:2282 - Invalid configuration (incorrect pin connections and/or modes) on block:<u_user_top/u_qdr_phy_top/u_phy_iob/u_phy_oserdes_wr/u_iodelay_addr>:<IODELAYE1_IODELAYE1>. 
With ODELAY_TYPE programming FIXED active input pins INC, RST and CE are not used and will be ignored.


The ODELAY_TYPE must be in FIXED mode as the MIG design provides a default ODELAY value on the address and control signals to ensure that they are center aligned with the write clocks K/K#.

In FIXED mode, the INC, CE, and RST signals are ignored because the ODELAY element uses only the value provided.

The MIG design is not connecting INC and CE inputs, but is connecting the RST pin which is why the warning occurs.

This warning can be safely ignored.

The RST pin will be unconnected starting in the ISE 13.2 software release.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 40741
Date Created 02/24/2011
Last Updated 08/18/2014
Status Active
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 12.4
  • MIG