When the MIG v3.61 V6 QDRII design is generated with all of the default options, it causes a BitGen DRC warning message in ISE Design Suite 12.4.
The ODELAY_TYPE=FIXED attribute for each IODELAYE1 being used in the MIG design causes the following warning during BitGen:
The ODELAY_TYPE must be in FIXED mode as the MIG design provides a default ODELAY value on the address and control signals to ensure that they are center aligned with the write clocks K/K#.
In FIXED mode, the INC, CE, and RST signals are ignored because the ODELAY element uses only the value provided.
The MIG design is not connecting INC and CE inputs, but is connecting the RST pin which is why the warning occurs.
This warning can be safely ignored.
The RST pin will be unconnected starting in the ISE 13.2 software release.