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It has been discovered that in Spartan-6 FPGA designs that utilize inputs implemented with split internal termination (UNTUNED_SPLIT_XX, where XX is 25, 50, or 75), no internal termination is enabled in hardware. Common indications that are observed include:
This issue does not impact bi-directional signals, so MIG/Memory interface-based designs are not typically affected.
For software versions prior to and including 13.2, the termination can be enabled by making a signal bi-directional with the 3-state control permanently enabled High (output disabled).
Note: the Save constraint must be utilized to avoid optimization back into an input.
This issue is resolved in ISE version 13.3. Later versions are free from this limitation.
Additional Notes:
Because the IN_TERM attribute is IOSTANDARD-independent, this issue can occur with many standards; most commonly this would be expected in SSTL, HSTL, and LVCMOS.
The issue is isolated to BitGen, so throughout the implementation process, the design would indicate that IN_TERM is appropriately enabled.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |
50932 | Xilinx SelectIO Solution Center - Design Advisory | N/A | N/A |
AR# 40818 | |
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Date | 01/06/2016 |
Status | Active |
Type | Design Advisory |
Devices |
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