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Xilinx Timing Analysis Solution Center

The Timing Analysis Solution Center is available to address all questions related to Xilinx Timing Analysis tools.

The Timing Analysis Solution Center provides information about the usage of tools and recommendations on how to troubleshoot a problem.

Documentation

Xilinx Timing Analysis Solution Center - Documentation

Please refer to the following documentation when running Timing Analysis.

NOTE: This answer record is part of the Xilinx Timing Analysis Solution Center (Xilinx Answer 40832). The Xilinx Timing Analysis Solution Center is available to address all questions related to Timing Analysis. Whether you try to setup timing constraint on a new design or troubleshooting a timing violation, use the Timing Analysis Solution Center to guide you to the right information.


Timing Analysis General Resources

  • Timing Analysis User Guide - UG612
  • Xilinx Constraint Guide - UG625
  • Xilinx Command Line Tool Guide - UG628

Design Advisories

Design Advisory for Xilinx Timing Solution Center

Design Advisory Answer Records are created for issues that are important to designs currently in progress and can be selected to be included in the Xilinx Alert Notification System.

Note: This Answer Record is part of the Xilinx Timing Analysis Solution Center (Xilinx Answer 40832). The Xilinx Timing Analysis Solution Center is available to address all questions related to Timing Analysis. Whether you are trying to setup timing constraint on a new design or troubleshooting a timing error, use the Timing Analysis Solution Center to guide you to the right information.

Please review (Xilinx Answer 42444) if you have a Virtex-6 FPGA design using Block RAM.

Please review (Xilinx Answer 47938) if you have a Virtex-6 FPGA design using I/O Standards on OPADs (Tioop/Tiotp).

Please review (Xilinx Answer 54230) if you have a Spartan-3a/Spartan-3an/Spartan-3e/Virtex-4/Virtex-5/6 series/7 series FPGA design using out-of-phase cross clock domain data paths.

Please review (Xilinx Answer 54246) if you have 7 series FPGA design using long wire routes.


Top Issues

Xilinx Timing Analysis Solution Center - Top Issues

The following answer records cover current known issues as well as commonly asked questions related to Timing Analysis.

NOTE: This answer record is part of the Xilinx Timing Analysis Solution Center (Xilinx Answer 40832). The Xilinx Timing Analysis Solution Center is available to address all questions related to Timing Analysis. Whether you are trying to setup timing constraint on a new design or troubleshooting a timing error, use the Timing AnalysisSolution Center to guide you to the right information.


Top Known Issues (by Version)

9.x
(Xilinx Answer 29069) - 9.1.03 Timing Analyzer - Timing error generated when MicroBlaze used in Spartan 3A-DSP

10.x
(Xilinx Answer 22481) - 10.1 Timing Analyzer - I cannot perform voltage and temperature pro-rating for Virtex-5. Why?
(Xilinx Answer 25309) - 10.1 Timing Analyzer - Cannot copy from HTML version of Timing Report
(Xilinx Answer 30018) - 10.1 Technology Viewer/Timing Analyzer Cross-Probing - LOCALBUF is not connected on the inputs in the cross-probed Translated Schematic/Exploration View
(Xilinx Answer 30043) - 10.1 Timing Analyzer - Cross-probe correlated path to tech view is empty
(Xilinx Answer 30335) - 10.1 Timing Analyzer/Constraints Editor/Floorplan Editor/PACE - Launching via command line causes multiple issues (crashes to incorrect files)
(Xilinx Answer 30505) - 10.1 Timing Analyzer - Closing Timing Analyzer produces temporary file names for unsaved reports
(Xilinx Answer 30508) - 10.1 Timing Analyzer - Timing Analyzer does not notify me when it is out of sync with UCF changes
(Xilinx Answer 30537) - 10.1 Timing Analysis/Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I do not have an MREG enabled in the Virtex-5 DSP48E?
(Xilinx Answer 30624) - 10.1 Timing Analyzer - Negative slack value on OFFSET OUT constraint results in "Invalid Slack Equation" dialog
(Xilinx Answer 31094) - 10.1 Timing Analyzer - FATAL_ERROR:Timing:bastwgraphedit.c:2262:1.36.2.4 with multiple FROM:TOs
(Xilinx Answer 31106) - 10.1 Timing Analyzer - Opening an old project with TA invokes multiple messages to use Project navigator to update project
(Xilinx Answer 31113) - 10.1 Timing Analyzer - I cannot cross probe from Timing Analyzer to Floorplan Implemented (FPI) or to Schematic viewer for several new parts
(Xilinx Answer 31114) - 10.1 Timing Analyzer - Context menu cross probe links for Floorplan Implemented (FPI) and Translated netlisd view are grayed out
(Xilinx Answer 31124) - 10.1 Timing Analyzer - Standalone version launches when TWX file is not specified
(Xilinx Answer 31530) - 10.1 Timing Analyzer - Links are not working in "Table of Timegroups" section of timing reports

11.x
(Xilinx Answer 17501) - 11.1 Timing Analyzer - Cross-probing does not work consistently with FPGA Editor
(Xilinx Answer 29885) - 11.1 Known Issue - Timing Analyzer - Misleading information in the Timing Improvement Wizard
(Xilinx Answer 30032) - 11.1 Known Issue - Timing Analyzer Crossprobing - Timing path does not show in Technology-Exploration window
(Xilinx Answer 30036) - 11.1 Known Issue - Timing Analyzer Crossprobing - Multiple path/connections shown through slice/BELs during xprobe to Floorplan/Schematic
(Xilinx Answer 30063) - 11.1 Known Issue - Constraints Editor/Timing Analyzer - Wrong timing constraint is edited when "Editing Constraints" from Timing Analyzer
(Xilinx Answer 30503) - 11.1 Known Issue, Timing Analyzer - Multiple UCF files do not show up in Timing Analyzer
(Xilinx Answer 30506) - 11.1 Known Issue - Timing Analyzer - Timing Analyzer fails to open Constraint Editor for a design with multiple UCF files
(Xilinx Answer 31798) - 11.1 Release Notes - Timing Analyzer - Timing Analyzer will not be supported in the 11.1 Tcl shell
(Xilinx Answer 32325) - 11.1 Known Issue - Timing Analysis, Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I use a CRC32 component?
(Xilinx Answer 32844) - 11.1 Timing Analyzer - "Saving to report" message stays in the console after saving is complete
(Xilinx Answer 32955) - 11.2 Timing Analyzer - Clock skew calculations ignores the PRIORITY keyword on the PERIOD constraint
(Xilinx Answer 33113) - 11.2 Timing Analyzer - Autogenerated constraints report incorrect value for clk to pad
(Xilinx Answer 33292) - 11.2 Timing Analyzer - Spartan-6 FPGA - Timing Analyzer reports large clock skew between LX25 and LX45
(Xilinx Answer 33765) - 11.1 Timing Analyzer - NET PERIOD clock arrival times change

Other
(Xilinx Answer 23298) - Virtex-4 ISERDES/OSERDES - RST recovery and removal time are not included in the data sheet or analyzed by the Timing Analyzer tool