We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40855

12.x/13.1 ChipScope - IBERT - Virtex-6 GTX attribute TERMINATION_OVRD set incorrectly to TRUE


In the IBERT core for Virtex-6 GTX the attributeTERMINATION_OVRDis set to TRUE with the attributeTERMINATION_CTRL set to 0x14.

TERMINATION_OVRD should be set to FALSE to use theexternal calibration resistor connected toMGTAVTTRCAL and MGTRREF pins.

Please see the Virtex-6 GTX user guide UG366 for more information.


The value can be changed in IBERT under the tab DRP Settings. A core fix will be included in ChipScope Pro tool 13.2

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35269 12.x ChipScope Pro - Known Issues for the ChipScope Pro 12.x software N/A N/A
AR# 40855
Date Created 04/08/2011
Last Updated 01/02/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ChipScope Pro - 12.4
  • ChipScope Pro - 13.1
  • ChipScope Pro IBERT for Virtex-6 GTX