AR# 40902 Virtex-6 FPGA GTH Transceiver - Updates for Production HXT, attributes, and initialization sequences
Description
Solution
1. Attribute Updates for Production Silicon:
Attribute and port updates that need to be made in the GTH wrapper for production silicon:
Attribute | Value | ||||||
PLL_CFG0[15:6] | 27Fh(1) | ||||||
PLL_CFG1 | 81C0h | ||||||
DLL_CFG0 | 8202h | ||||||
MISC_CFG | 0008h | ||||||
RX_CFG0_LANE<n> | 0500h | ||||||
RX_CFG1_LANE<n> | 821Fh | ||||||
RX_CFG2_LANE<n> | 1001h | ||||||
RX_CTLE_CTRL_LANE<n> | [7:4] = ctle_peak ctle_peak is a function of channel loss. ctle_peak (decimal) = 3 + 1 code for every 0.5 dB channel loss at Nyquist Default: 008Fh (assuming 2.5 dB channel loss) | ||||||
RX_CDR_CTRL1_LANE<n> | 4200h | ||||||
RX_PI_CTRL0 | D2F0h | ||||||
TERM_CTRL_LANE<n> | 5007h | ||||||
TX_CFG0_LANE<n> | 203Dh | ||||||
TX_PREEMPH_LANE<n> | [7:4] = post_cursor [3:0] = pre_cursor pre/post_cursor settings are channel dependent Default: 00A1h | ||||||
PCS_MISC_CFG_0_LANE<n> | 1116h when TXRATE = 2'b00 1117h when TXRATE = 2'b01 1114h when TXRATE=2'b10 1114h when TXRATE=2'b11 | ||||||
LANE_PWR_CTRL_LANE<n> | 0400h | ||||||
RX_LOOP_CTRL_LANE<n> | 007Fh | ||||||
RX_AEQ_VAL0_LANE<n> | 03C0h | ||||||
RX_AEQ_VAL1_LANE<n> | 0000h Setting DFE in AUTO mode | ||||||
RX_AGC_CTRL_LANE<n> | [15:6]: Reserved, tie to 10'h0 [5]: AGC manual enable [4:0]: AGC manual value (depends on transmit signal amplitude and channel differential insertion loss) The following recommendation is for channel differential insertion loss less than 8 dB
(*) If acceptable BER is not achieved, please use the Full Range setting In most cases GTH works in short reach and a swing higher than 450mV pkpk is expected - this is the reason why the AGC has been set to "auto mode" as default: 0000h | ||||||
| TX_CFG1_LANE<n> | 0F00h | ||||||
| TX_CLK_SEL1_LANE<n> | 2121h | ||||||
| TX_CFG2_LANE<n> | 0081h when TXRATE = 2'b00 0001h for other values of TXRATE |
Notes:
- Bits [5:0] represent the feedback divider of the PLL in the GTH Quad, which should be set based on the recommendations in the GTH Users Guide (UG371), see the PLL Settings for Common Protocols section.
| Attribute | PMA Loopback | Other modes (DEFAULT) |
PMA_LPBK_CTRL_LANE<n>[1:0] | 2'b10 | 2'b00 |
| SLICE_CFG | 0003h | 0000h |
| LANE_AMON_SEL | 0100h | 00F0h |
The attribute and port updates noted above for production silicon are generated natively by the Virtex-6 FPGA GTH Transceiver Wizard version v1.8 released officially with ISE Design Suite 13.1 Update.
Please note that these attribute settings can only be used with production silicon and not ES. The bitstreams for production silicon cannot be used with ES and vice-versa.
2. Updated Initialization Sequence for Production Silicon:
The following timing diagrams illustrate the initialization sequence that should be followed after either power up or a GTHRESET has been issued to the transceiver:
An early version of the initialization code for production silicon that is generated by the Wizard is available in the links below. This is generated natively by the Virtex-6 FPGA GTH Transceiver Wizard version v1.8 released officially with ISE Design Suite 13.1 Update.
Code:
Verilog: v6_gthwizard_v1_6_gth_reset.v
VHDL: v6_gthwizard_v1_6_gth_reset.vhd
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