UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 40985

12.4/13.4.14.7 Pack - WARNING:Pack:1542: The register xxx has the property IOB=TRUE ...

Description

My design is getting the following warning message for an input Flip-Flop.

It was successfully packed into the input IOB.

Why is this warning message about an "output register" being printed?
 
 

WARNING:Pack:1542 - The register sharc/adsp_hbg_n_r has the property IOB=TRUE,
   but was not packed into the output side of an I/O component. The output
   register symbol "sharc/adsp_hbg_n_r" has loads outside the I/O component.
   The output register symbol "sharc/adsp_hbg_n_r" has loads outside the I/O
   component.

Solution

In this case, the Flip-Flop which is driven by an input buffer also has output buffer connectivity because it drives the 3-state enable pins of several OBUFTs.

Although the designer considered it to be an input Flip-Flop only, the tools also evaluated it for an output IOB pack.

That is why a warning message about the failed output IOB pack is printed despite the successful input IOB pack.
AR# 40985
Date Created 03/04/2011
Last Updated 09/10/2014
Status Active
Type Error Message
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite - 14
  • ISE Design Suite - 13
  • ISE Design Suite - 12