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AR# 41051 Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 128-bit Transmit Interface May Drop Single Cycle Packets

Description

Version Found: v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45723).

When using the x8 Gen 2 128-bit AXI Streaminginterface, it is possible that some packets presented by the user on the transmit interface may be lost.

Solution

This problem only affects single cycle packets meaning that the entire TLP is transmitted on one clock cycle on the 128-bit interface. Also, it will only occur if there is an incoming configuration transaction at the same time the packet is presented. Xilinx is currently investigating this issue and this answer record will be updated once a workaround is available.

This issue does not affectthe 64-bit AXI interface or the legacy 128-bit TRN interface.

Revision History
01/18/2012 - Updated; added reference to 45723
03/03/2011 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45723 Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions N/A N/A

Actions

AR# 41051
Date Created 03/04/2011
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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