Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
In simulation, the 7 Series Integrated Block Wrapper takes about 75 microseconds to link up when I use the provided testbench example design.
Is this right?
A change can be made to the "pcie_gtx_7x.v" filefound in the generated core's source directory. With this change, the core links up at about 35 microseconds.
This change is going to be incorporated into the next update of the core. The current logic is fine and either way has no impact on hardware operation.
Change the followingline:
assign phy_rdy_n = !(&plllkdet[NO_OF_LANES-1:0] & clock_locked);
assign phy_rdy_n = (&phystatus_rst[NO_OF_LANES-1:0] & clock_locked);
12/06/2011 - Added version resolved reference to Answer Record 40469
03/03/2011 - Initial Release