AR# 41083 Design Advisory for Spartan-6 IODELAY2 - IODELAY2 Data Rate and Corresponding Bit Error Rates for New Mask Revision Silicon
Description
The Spartan-6 Production Errata (EN148) details maximum data rates for the Spartan-6 FPGAIODELAY2 element in order to avoid data loss for New Mask Revision silicon. If some amount of data loss may be acceptable to a design, this answer record gives more information to assist in that analysis.
This answer record does not apply to Previous Mask Revision devices (for information onhow to identify new mask revisions, see errata EN148 or PCN XCN11012).For Previous Mask Revision devices, see (Xilinx Answer 38408). XA Automotive, XQ, Q grade, andXC Lower Power -1L devices will be released with the New Mask Revision only.
Solution
Single Data Bit Corruption in IDELAY and ODELAY Modes
The IODELAY2 block can corrupt a single data bit for some IDELAY_VALUE and ODELAY_VALUE settings.
Work-arounds
IDELAY_TYPE=FIXED, VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX or DIFF_PHASE_DETECTOR, or when used in ODELAY mode
Limit the data rate through the IODELAY2 to the maximum specifications in Table 2.
IDELAY_TYPE=FIXED or VARIABLE_FROM_ZERO or when used in ODELAY mode, with tap limit
When using a fixed tap value and requiring higher performance than specified in Table 2, restricting the maximum IDELAY_VALUE or ODELAY_VALUE can avoid data corruption at the higher indicated data rates. Table 3 provides a summary of these higher data rates for fixed tap values.
Work-around: Error Rates for Operation Outside of Maximum Data Rates
When using the standard VCCINT operating range (1.14 to 1.26 volts), higher data rates may be required than those given above and in EN148. The user can potentially trade off data rate against the possibility of data loss. Numbers are given in Table 4 and Table 5 below for various data rates and for the MTBF (Mean Time Before Failure) and corresponding BER (Bit Error Rate) for all speed and temperature grades. The BERs, while very low, are statistically non-zero and it is up to the designer as to whether an application can tolerate the given error rate. The numbers are given per IODELAY2 element (a master and a slave acting together in differential phase detector mode count as one IODELAY2) and should be multiplied by the number of data lines being received in the application to get an overall BER.Table 4: MTBF and BER for I and Q Temperature Grade with New Mask Revision Silicon
MTBF (seconds) |
BER | ||||
Data Rate (Mbps) |
Bit Period (pS) |
-3I/Q |
-2I/Q |
-3I/Q |
-2I/Q |
667 |
1499 |
Not Applicable |
2.0 x 1027 |
Not Applicable |
7.5 x 10-37 |
750 |
1333 |
1.0 x 1033 |
1.0 x 1022 |
1.3 x 10-42 |
1.3 x 10-31 |
800 |
1250 |
2.0 x 1028 |
3.0 x 1018 |
6.2 x 10-38 |
4.2 x 10-28 |
950 |
1053 |
1.0 x 1018 |
1.0 x 1011 |
1.0 x 10-27 |
1.0 x 10-20 |
1050 |
952 |
8.0 x 1012 |
8.0 x 106 |
1.2 x 10-22 |
1.2 x 10-16 |
1080 |
926 |
2.0 x 1011 |
5.0 x 105 |
4.6 x 10-21 |
1.8 x 10-15 |
Table 5: MTBF and BER for C Temperature Grade with New Mask Revision Silicon
MTBF (seconds) |
BER | ||||
Data Rate (Mbps) |
Bit Period (pS) |
-3C |
-2C |
-3C |
-2C |
750 |
1333 |
Not Applicable |
5.0 x 1023 |
Not Applicable |
2.7 x 10-33 |
800 |
1250 |
Not Applicable |
1.5 x 1020 |
Not Applicable |
8.3 x 10-30 |
950 |
1053 |
5.0 x 1019 |
5.0 x 1012 |
2.1 x 10-29 |
2.1 x 10-22 |
1050 |
952 |
4.0 x 1014 |
4.0 x 106 |
2.4 x 10-24 |
2.4 x 10-18 |
1080 |
926 |
1.0 x 1013 |
2.5 x 107 |
9.3 x 10-23 |
3.7 x 10-17 |
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46791 | Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems | N/A | N/A |
| 38408 | Design Advisory for Spartan-6 - IODELAY2; Late and Early Edge Delays and Single Data Bit Corruption | N/A | N/A |
| 39046 | Spartan-6 IODELAY2 - Late Data Edge and Early Data Edge Timing Analysis | N/A | N/A |
| 34856 | Design Advisory Master Answer Record for Spartan-6 FPGA | N/A | N/A |