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AR# 41196

13.1 Speeds Files - BUFIO2FB failing component switching limits


The following component switching limit violation relating to BUFIOFB is observed in ISE 13.1 software.

Component Switching Limit Checks: PERIOD analysis for net "DisplayDeserialiser/LVDSSampleClock" derived from

PERIOD analysis for net "DisplayDeserialiser/DisplayReceiverPLL_CLKOUT1" derived from NET "DisplayDeserialiser/DisplayReceiverPLL/clkin1" PERIOD = 7.14 ns HIGH 50%; divided by 7.00 to 1.020 nS
duty cycle corrected to 1.020 nS HIGH 510 pS

Slack: -0.884ns (period - min period limit)
Period: 1.020ns
Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
Physical resource: DisplayDeserialiser/DisplayReceiverPLLFeedbackBuffer/I
Logical resource: DisplayDeserialiser/DisplayReceiverPLLFeedbackBuffer/I
Location pin: BUFIO2FB_X1Y8.I
Clock network: DisplayDeserialiser/LVDSSampleClock

Is this a known issue?


This issue is scheduled to be fixed in the next major release of software.
AR# 41196
Date 04/11/2011
Status Active
Type Known Issues
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • ISE Design Suite - 13.1
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