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AR# 41200

SPI-4.2 - Updated Virtex-7 device Sink Core performance and Virtex-7 and Kintex-7 Sink and Source Core MMCM settings for using Global Clocking


When global clocking is used for the SPI-4.2, the Sink core performance for Virtex-7 devices has been updated and is shown below. The Sink and Source core Virtex-7 and Kintex-7 MMCMs should also be update to ensure that the Bandwidth is set to "HIGH". The SPI-4.2 v11.2 core scheduled to be released in ISE 13.2 software will be updated to reflect these changes.


Supported Virtex-7 FPGA Sink Core Performance and Clocking Schemes

Speed Grade
<=900Mbps 1Gbps 1.1Gbps 1.2Gbps 1.25Gbps
-1 Regional/Global
Regional only*
Regional only*
-2 Regional/Global
Regional Only*
-3 Regional/Global
Regional/Global Regional/Global

*Note the Clocking schemes marked with a '*' have been updated since the SPI-4.2 v11.1 release in ISE13.1

For Virtex-7 and Kintex-7 devices, the SysClk and SnkClk MMCM bandwidth should be changed from "Optimized" to "High" to ensure low output jitter.

For a specific frequency and speed grade, it might be possible to generate more optimal MMCM settings than the default provided with the core. It is recommended that users use the latest LogiCORE Clocking Wizard IP to generate the optimum MMCM instantiation for their specific data rate; see (Xilinx Answer 39432) for step-by-step guidance on how to generate an MMCM instantiation for the SPI-4.2 core using the Clocking Wizard IP.

AR# 41200
Date Created 03/14/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • SPI-4 Phase 2 Interface Solutions