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AR# 41202

13.1 PlanAhead - Import Synplify project does not import source files

Description

In the PlanAhead tool, I select File -> New Project to invoked the New Project Wizard to create a new project. Under "Specify RTL Sources", I specified the "Import settings from XST or Synplify project" option. After selecting my Synplify (Pro) project and finishing the New Project Wizard, none of the Synplify project source files are added to the PlanAhead project.

Is this expected behavior ?

How do you import the files?

Solution

The source files are not being added because the ".prj" file does not specify a type for the files. This is legal according to the Synplify documentation, and PlanAhead should infer the file type from the extension according to the following rules:
  • The -filetype argument overrides automatic filename extension placement.
  • The following extensions should be interpreted as indicated below:
    1. .adc -analysis_constraint Analysis Design Constraint
    2. .edf, .edn -edif EDIF .sdc -constraint Constraint
    3. .sv1 -verilog Verilog
    4. .tcl -tcl Tcl Script
    5. .v -verilog Verilog
    6. .vhd, .vhdl -vhdl VHDL
    7. any -_include Include
    8. 1. Use the .sv format for SystemVerilog keywords support. Both Verilog and SystemVerilog formats are added to the Verilog folder.

This issue is scheduled to be fixed in ISE Design Suite 13.2.

To allow the Synplify project to be read by PlanAhead 13.1, edit the ".prj" file and add the -filetype for each file.

Example:

Change the following section from:

##add_file options
add_file -verilog {C:/Synopsys/fpga_D201003SP1/bin/../lib/xilinx/unisim.v}
add_file {ipcore_dir/tenths.vhd}
add_file {smallcntr.vhd}
add_file {statmach.vhd}
add_file {ipcore_dir/tenths.ngc}
add_file {dcm1.vhd}
add_file {hex2led.vhd}
add_file {decode.vhd}
add_file {cnt60.vhd}

To:

##add_file options
add_file -verilog {C:/Synopsys/fpga_D201003SP1/bin/../lib/xilinx/unisim.v}
add_file -vhdl {ipcore_dir/tenths.vhd}
add_file -vhdl {smallcntr.vhd}
add_file -vhdl {statmach.vhd}
add_file -vhdl {ipcore_dir/tenths.ngc}
add_file -vhdl {dcm1.vhd}
add_file -vhdl {hex2led.vhd}
add_file -vhdl {decode.vhd}
add_file -vhdl {cnt60.vhd}


AR# 41202
Date Created 03/15/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Tools
  • PlanAhead - 13.1